I haven't tried the memory yet.I found the relevant parameters to be determined by
examination either of the manual or the schematic.
Meanwhile, I'm delaying release of the HDMI encoder until I've made the method
of implementation more accessible as a library part. The efficiency arises from
arranging for pairs of signals to fit into LUT6_2s, and by putting a nice fit into
a CARRY4 for the running disparity.
The running disparity needs a 4-bit counter (as the low bit in the 5-bit implementation
is stuck and so is ignored). One needs to add or subtract constants from -5 to +5 to
it. So it can be thought of as an increment circuit with 4 control signals.
This fits nicely into a slice. The general slice I've created (but not fully tested)
has a single std_logic_vector input that gives the number being incremented
(or loaded), a std_logic_vector(3 downto 0) that controls what operation is
done, a 16-wide string that defines the16 operations (add or load), and an
array of 16 integers that give the constants to either load or add. (To subtract,
you use 2s complement / mess with carry-in).
For the DDR SDRAM, the .xco values I used were:
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_Virtex6_and_Spartan6 family Xilinx,_Inc. 3.7
# END Select
# BEGIN Parameters
CSET component_name=DDRSDRAM
CSET xml_input_file=./DDRSDRAM/user_design/mig.prj
# END Parameters
GENERATE
# CRC: 4f566fd2
and datasheet.txt:
CORE Generator Options:
Target Device : xc6slx45-csg324
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : DDRSDRAM
No of Controllers : 1
Hardware Test Bench : disabled
Controller Options :
Memory : DDR2_SDRAM
Design Clock Frequency : 2500 ps (400.00 MHz)
Memory Type : Components
Memory Part : MT47H64M16XX-25E
Equivalent Part(s) : MT47H64M16HR-25E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 4(010)
CAS Latency : 5
DQS# Enable : Enable
DLL Enable : Enable-Normal
OCD Operation : OCD Exit
Output Drive Strength : Reducedstrength
Outputs : Enable
Additive Latency (AL) : 0
RDQS Enable : Disable
RTT (nominal) - ODT : 50ohms
High Temparature Self Refresh Rate : Disable
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : CALIB_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended
