06-07-2011 01:28 PM
I'm designing for the Atlys board; expect to pick one up in a week or two.
A difference from the reference design is that I'm running the video logic at twice the pixel clock frequency. The reason for doing this is that this frequency is needed anyway for the OSERDES to work and so it eliminates a clock domain. It also eliminates the video FIFO that converts from pixel frequency to twice pixel frequency.
Which reminds me, can't you remove that FIFO by simply putting a circuit to ship DDR pixels at the pixel rate frequency? To do this, one has to get the pixel clock into the fabric (i.e. off of the BUFG clock paths so that it can be used in regular logic). One does this with a toggle, registering at the falling clock, and then take the XOR function between the two registers.
Before I redid the logic so that the system ran at twice the pixel frequency, I redid the HDMI encoder to use 1/3 of the area. This replaces the "encode.v" from XAPP495 with VEncode.vhdl and DISPCNTR.SCH (schematic). The basic idea was to analyze the algorithm mathematically, eliminate redundant logic, and design to the two-output LUT-6 structure of Spartan-6 CLBs. Anyone interested I'll post the files.
07-05-2011 11:34 PM
Did you manage to run DDR2 controller generated from MIG on Atlys? -- what are the MIG settings / parmeters for terminations etc? Can you share those?
What read / write bandwidth you could obtain? - I have been asking these things to Atlys support never got a substantial answer.
07-06-2011 10:26 AM
I haven't tried the memory yet.I found the relevant parameters to be determined by
examination either of the manual or the schematic.
Meanwhile, I'm delaying release of the HDMI encoder until I've made the method
of implementation more accessible as a library part. The efficiency arises from
arranging for pairs of signals to fit into LUT6_2s, and by putting a nice fit into
a CARRY4 for the running disparity.
The running disparity needs a 4-bit counter (as the low bit in the 5-bit implementation
is stuck and so is ignored). One needs to add or subtract constants from -5 to +5 to
it. So it can be thought of as an increment circuit with 4 control signals.
This fits nicely into a slice. The general slice I've created (but not fully tested)
has a single std_logic_vector input that gives the number being incremented
(or loaded), a std_logic_vector(3 downto 0) that controls what operation is
done, a 16-wide string that defines the16 operations (add or load), and an
array of 16 integers that give the constants to either load or add. (To subtract,
you use 2s complement / mess with carry-in).
For the DDR SDRAM, the .xco values I used were:
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG_Virtex6_and_Spartan6 family Xilinx,_Inc. 3.7
# END Select
# BEGIN Parameters
# END Parameters
# CRC: 4f566fd2
CORE Generator Options:
Target Device : xc6slx45-csg324
Speed Grade : -3
HDL : vhdl
Synthesis Tool : Foundation_ISE
MIG Output Options:
Component Name : DDRSDRAM
No of Controllers : 1
Hardware Test Bench : disabled
Controller Options :
Memory : DDR2_SDRAM
Design Clock Frequency : 2500 ps (400.00 MHz)
Memory Type : Components
Memory Part : MT47H64M16XX-25E
Equivalent Part(s) : MT47H64M16HR-25E
Row Address : 13
Column Address : 10
Bank Address : 3
Data Mask : enabled
Memory Options :
Burst Length : 4(010)
CAS Latency : 5
DQS# Enable : Enable
DLL Enable : Enable-Normal
OCD Operation : OCD Exit
Output Drive Strength : Reducedstrength
Outputs : Enable
Additive Latency (AL) : 0
RDQS Enable : Disable
RTT (nominal) - ODT : 50ohms
High Temparature Self Refresh Rate : Disable
FPGA Options :
Class for Address and Control : II
Class for Data : II
Memory Interface Pin Termination : CALIB_TERM
DQ/DQS : 25 Ohms
Bypass Calibration : enabled
Debug Signals for Memory Controller : Disable
Input Clock Type : Single-Ended
11-28-2011 11:07 PM
I am using Digilent Atlys board inorder to learn the EDK flow and getting familiar with various IP cores in EDK.
While trying to use UART core, I am stuck in getting the value out from Hyperterminal.
I tried using the 'hello world.c' application and also tried to use a customized IP from whre I am pumping some predefined value onto UART. But nothing show any result. Sometimes I got some junk characters coming but its only with some builds.
Well, can you help me fixing this. At this point I was some clear documentation which can tell me how to use Atlys board inorder to bring up the UART.
I welcome any idea on this problem. Please mark a copy to my below email.
mail id: firstname.lastname@example.org
05-20-2013 02:46 PM
I need information about using the HDMI port for getting data in and out.I am using atlys spartan 6 FPGA (LXS45). How did you go about it?
Also, I am using ISE webpack 14.5.