3rd Party/Other Boards and Kits

[sraf16]

Sorry for the naive question (I’m uninitiated to FPGA design), but how to use the files that come with XAPP495, to implement and run with ISE 13.3, to view the images via HDMI output port onto the monitor witch my Atlys Spartan-6 FPGA Board?

[eteam00]

1.  Your first support resource should be Digilent (including the Digilent user forums).  I'm not a Digilent customer, so I have no personal experience with their support resources.

2.  In these forums, user joelby has been a valuable resource for the care and feeding of the Digilent ATLYS board.  I suggest you search these forums for existing posts written by joelby, particularly ones which include references to ATLYS, HDMI, or XAPP495.  See if this search link is useful, and turns up some useful information.

-- Bob Elkind

[joelby]

I felt a tingling sensation in my Atlys board, and then saw that this thread had been posted.

From memory, you need to do the following:

• Create a new project in ISE. Set the device to XC6SLX45-CSG324, speed grade -3.
• Add all of the Verilog (.v) files in the XAPP495 distribution to the project.
• Set either vtc_demo.v (colour bar generator) or dvi_demo.v (2x2 switch matrix) as the top module by right-clicking and selecting "Set as Top Module"
• I don't think that ISE can handle multiple UCF files, so either add dvi_demo.ucf or vtc_demo.ucf to the project, depending on the demo you want to try.
• Select the top module and Generate Programming File.

The vtc_demo should cause you no woe, but dvi_demo will probably require some reconfiguration of jumpers on the Atlys for it to work:

• Add jumper JP5 to enable HDMI input on J1
• Install jumpers JP6/JP7 to enable SDA/SCL pass through from J3.
• Install jumpers on the anonymous header labelled SDA/SCL next to J1 (they're called JP2 on the schematic, though). On the boards I've seen and heard about, these were supplied from the factory with jumpers connected, but installed incorrectly, shorting SDA and SCL together on both sides rather than passing them through. Check the schematic diagram to see if this applies to you and then rotate them if necessary.

Even with this, you might have some problems with dvi_demo - have a look at some of the threads in the search results that Bob linked.

[sraf16]

Joelby, 

Thanks a lot for your help !!.

[gszakacs]

I don't think that ISE can handle multiple UCF files,...

ISE allows multiple .ucf files for a project since at least version 10.1

However there is nothing available to conditionally use particular .ucf files, so you should only add

those .ucf files that correspond to the code you're building.

There was a recent thread on the subject of conditional .ucf file inclusion, but no response from

Xilinx on its intention to implement this.

-- Gabor

[joelby]

Fair enough! Yeah, I figured you could add more than one (does it just concatenate them?), but had never seen anything akin to 'Set as Active UCF' or similar.

If you're feeling inspired and intend to spend a lot of time studying both of the XAPP495 examples, perhaps create two projects - one for vtc_demo and one for dvi_demo, and only add those files that each requires (UCF in particular - the others will just be ignored if they're not used).

[gszakacs]

I suppose you could say that UCF files are concatenated, because the effect is the same.  All

UCF files added to the design are associated to the top level module.

Strangely, in earlier versions of ISE where you could only have one UCF file, there was the

concept of associating the UCF with any module in the project.  That would make a lot

more sense with multiple UCF's especially if modules can be included conditionally.

By the way, I wholeheartedly agree to making separate projects for the two designs.  ISE

allows you to change the top level module within a project, but I've noticed some side-effects

from doing this, including losing the UCF file (it still shows in the hierarchy view but becomes

detached from the project).  When that happens I usually have to delete it from the project and

then add it back in.

-- Gabor

[ywu]

Maybe give PlanAhead (PA) RTL flow a try. In PlanAhead you can create multiple constraint sets and multiple synthesis/implementation runs and choose which constraint set goes with which run. Make sure you use the latest PA (13.3) as lots of features/improvements have been made to PA RTL flow in the past couple releases.

---

gszakacs wrote:

I suppose you could say that UCF files are concatenated, because the effect is the same.  All

UCF files added to the design are associated to the top level module.

Strangely, in earlier versions of ISE where you could only have one UCF file, there was the

concept of associating the UCF with any module in the project.  That would make a lot

more sense with multiple UCF's especially if modules can be included conditionally.

By the way, I wholeheartedly agree to making separate projects for the two designs.  ISE

allows you to change the top level module within a project, but I've noticed some side-effects

from doing this, including losing the UCF file (it still shows in the hierarchy view but becomes

detached from the project).  When that happens I usually have to delete it from the project and

then add it back in.

-- Gabor

---

[sraf16]

Hi! Joelby, as you have mentioned earlier I have:

• created a new ISE project.
• added all of the .v files from XAPP495.
• added vtc_demo.ucf.
• set vtc_demo as the top module.
• generated a programming file.

But here, the vtc_demo gives 6 errors like that:

• ERROR:MapLib:30 - LOC constraint D8 on TMDS<0> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

• ERROR:MapLib:30 - LOC constraint C8 on TMDSB<0> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

• ERROR:MapLib:30 - LOC constraint A7 on TMDSB<1> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

• ERROR:MapLib:30 - LOC constraint C14 on SW<2> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

• ERROR:MapLib:30 - LOC constraint D14 on SW<1> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

• ERROR:MapLib:30 - LOC constraint B11 on DEBUG<1> is invalid: No such site on the

device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.

 Please help!!.

[gszakacs]

Those errors mean that the UCF file doesn't match the FPGA part type selected in the project settings.

If the UCF file was made specifically for your board, then the problem is most likely that you selected

the wrong part or package in the project settings.  In the ISE Navigator menu bar go to:

Project --> Design properties...

Make sure you set the part to

Family: Spartan 6

Device XC6SLX45

Package CSG324

Speed -3

From Joelby's first post:

• Create a new project in ISE. Set the device to XC6SLX45-CSG324, speed grade -3.

-- Gabor