3rd Party/Other Boards and Kits

[ciaoci]

Hi all,

I know this topic have been discussed but for my point of view (or my need) partially solved...

I have 8 boards mounting one Xilinx Virtex II PRO FPGAs with each its xcf32p FLASH PROM, I would like to make a JTAG chain with which load the bit file of each FPGA selecting the target via IMPACT tool.

I have done a cable propagating following signal:

                                                            B1                  B2                 B3       ..........               B8                     

                             VREF     ---->      VREF   --->  VREF   --->  VREF                   --->  VREF     

   JTAG-USB       GND      ---->      GND    --->  GND    --->  GND                     --->  GND

                             TCK       ---->      TCK     --->   TCK     --->   TCK                    --->  TCK

XILINX CABLE                                TDO    -_      TDO    -_      TDO  ---....___            TDO  ---------

                             TDI         ---->      TDI          ->  TDI          ->  TDI                    ----->  TDI               |

                             TMS       ---->      TMS    ---->  TMS    ---->  TMS                     ---->  TMS             |

                                                                                                                                                                 |

                             TDO  <------------------------------------------------------------------------------------------

Hope the graph is printed clear, anyway here a caption:

TDI signal escaping from the cable in input to the TDI signal of the first board, on that board, the TDO goes in input to the TDI of the bext board, and so on till the last board where the TDO go back to the cable TDO.

TCK and TMS signals are common to all devices, and the same I have done for the GND and (maybe wrong) for the VREF signal.

This last connection (VREF) I'm not sure is correct because seems to power on every FPGA chip when the first chip has been powered and the other not yet.

What is the right connection for signal VREF? I need to connect just to the first and do not propagate it?

Any recommendation on cable/wires length?

Cheers and thanks for any answers

[ciaoci]

Hi all,

I know this topic have been discussed but for my point of view (or my need) partially solved...

I have 8 boards mounting one Xilinx Virtex II PRO FPGAs with each its xcf32p FLASH PROM, I would like to make a JTAG chain with which load the bit file of each FPGA selecting the target via IMPACT tool.

I have done a cable propagating following signal:

                                                            B1                  B2                 B3       ..........               B8                     

                             VREF     ---->      VREF   --->  VREF   --->  VREF                   --->  VREF     

   JTAG-USB       GND      ---->      GND    --->  GND    --->  GND                     --->  GND

                             TCK       ---->      TCK     --->   TCK     --->   TCK                    --->  TCK

XILINX CABLE                                TDO    -_      TDO    -_      TDO  ---....___            TDO  ---------

                             TDI         ---->      TDI          ->  TDI          ->  TDI                    ----->  TDI               |

                             TMS       ---->      TMS    ---->  TMS    ---->  TMS                     ---->  TMS             |

                                                                                                                                                                 |

                             TDO  <------------------------------------------------------------------------------------------

Hope the graph is printed clear, anyway here a caption:

TDI signal escaping from the cable in input to the TDI signal of the first board, on that board, the TDO goes in input to the TDI of the bext board, and so on till the last board where the TDO go back to the cable TDO.

TCK and TMS signals are common to all devices, and the same I have done for the GND and (maybe wrong) for the VREF signal.

This last connection (VREF) I'm not sure is correct because seems to power on every FPGA chip when the first chip has been powered and the other not yet.

What is the right connection for signal VREF? I need to connect just to the first and do not propagate it?

Any recommendation on cable/wires length?

Cheers and thanks for any answers

[austin]

c,

Vref needs only to be connected to the first device, as it sets the voltage levels for the interface.

Check that all devices use the same voltage (probably 3.3v for v2 pro), otherwise you will need level shifters.

The clock signal integrity is important, glitches, ringing, overshoot and undershoot will cause problems.  Simulating the wiring with the loads, and the actual cable lengths in a tool like Hyperlynx will insure sucess.

[ciaoci]

I have cut the red wire....at the moment I see only many messages on IMPACT showing "Found many unknown devices..."  :(

In each board there is the flash and the v2 pro, I have read from the datasheet of the xcf32p that maybe it works at 1.8 voltage while I don't know the voltage of the v2 pro (could be 1.5V?!). Anyway I think that the board should be provided with their own regulator...or not? Using the jtag with just one board it works...

Cheers

[austin]

c,

The JTAG for V2Pro operates from 3.3v, so that is the voltage for that part.  If it is already on a board with other parts, and there is one JTAG port, then someone has already engineered all the level shifting, and signal integrity.

Can you daisy chain board JTAG ports?

Yes.  All the boards should be 3.3v (or else you are back to level shifters again), and you need to simulate the swignal integrity of cennecting all the cables up.  Reflections and mis-matches in impedances will cause the chain to fail at some point, or not work at all.

[ciaoci]

Solved using a signal repeater...

[thomas1974]

In addition to that solution, I like to state that I regularly use clock buffers to refresh the signals when I use more than 4-6 FPGAs per board in one chain, and one buffer per board (as said above).