04-09-2012 02:30 PM
The sim model is still there. Go here: http://www.micron.com/parts/psram/cellularram/mt45
In any event, I'm home now, so in the next few minutes I'll look at packaging up my sample code for you.
04-09-2012 03:13 PM
OK, here's a ZIP containing a few goodies:
1) The AsyncPSRAM.v module which provides a simple interface to reading/writing the Nexys-3 PSRAM in async mode. You may need to modify the number of waitstates in the state machine if you use an input clock frequency other than 100Mhz to this module.
2) A module which makes it easy to output values on the seven-segment display (in VHDL, everything else is in Verilog.)
Also note that the ISE archiver grabbed the module required for simulating the PSRAM but it claims it won't restore it to the right directory since it was external to the rest of the project. You should just remove it from the project once you load it in ISE and then re-add it to the project whereever you wind up putting it, if you care about the simulation.
If you manage to successfully integrate this with your project, I will be interested to hear what was wrong with the code you tried to write, by comparison. (I would also be happy if someone else is succesful in making use of my code. :-) )
04-10-2012 05:40 AM
:-) The problem is solved, How ridiculous! All the things about the timing are right. The key lies in Pin constraint. In the sch of nexys3 I found that the data0 of the Psram was connect to another chip the PIC Microcontroller, so I think it couldn't be used for the FPGA, the same is data1 and data 2.so I only connect to the psram with data3..15.
after I study the sch carefully I found that data0..2 was also connect to the fpga.So i add the three pins.And the problem wad solved.All the leds are blinking happly :-)
Here comes my timing and code,maybe these would be helpful to newer of fpga.
By the way,I try to add the verilog psram to my code,but the xst can't Synthesis
it doesn't support real, and can't recognize the word ‘function’ :-(
04-10-2012 07:47 AM