02-21-2012 10:03 PM
i try to run xapp495 in ise 12.1.i follow all instruction.add all .v source beside ucf file.(i work with vtc demo not dvi one)
and make vtc_demo the top module.
but when i run my progrm it give me error and warning in map part.
i cant understand the eroor nor why it give me them?
i download this program from xillinx site and it say it must work.
but should i change some setting or add some code before run it to make it work?
thank you in advance
and sorry for my bad eng.
and plz help me because it is very very urgent and i have a little time left.
some of the error and warnning
WARNING:Timing:3159 - The DCM, PCLK_GEN_INST, has the attribute DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists
between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths between these clock domains must be constrained using
WARNING:Timing:3159 - The DCM, PCLK_GEN_INST, has the attribute
DFS_OSCILLATOR_MODE not set to PHASE_FREQ_LOCK. No phase relationship exists
between the input clock and CLKFX or CLKFX180 outputs of this DCM. Data paths
between these clock domains must be constrained using FROM/TO constraints.
Due to other FF/Latch trimming, FF/Latch <Vregion_3> (without init value) has a constant value of 0 in block <hdcolorbar>. This FF/Latch will be trimmed during the optimization process.
thank you again
02-21-2012 11:34 PM
Don't forget to add the vtc_demo.ucf to the project (but not dvi_demo.ucf).
You shouldn't need to do anything else to make the demo work. The warnings you shared are just warnings and not errors. Did ISE successfully produce a .bit file? If so, it should all be fine (unless you didn't have vtc_demo.ucf in the project).
If you got an error and bit file generation failed, please let us know what the errors were.
02-22-2012 12:17 AM
yah i add vtc_demo ucf file
it cant map or place and route but when i run generate programming file separately it build .bit file
howover it dosent useful because when i compile it on atlys-spartan 6 it doesn't show anything in monitor.
they aren't error but they prevent compiler for compile successfully
02-22-2012 07:50 PM
Which HDMI port on the Atlys have you connected your monitor to? Have you tried fiddling with the switches that set the video mode?
Have you been able to run other designs on the board successfully?
If you think there's a problem with your tools, I can generate a bit file from the reference design, test in on my board, and email it to you if you send me your email address in a private message.