Sign In

Don't have a Xilinx account yet?

  • Choose to receive important news and product information
  • Gain access to special content
  • Personalize your web experience on Xilinx.com

Create Account

Username

Password

Forgot your password?
XClose Panel
Xilinx Home
Reply
Visitor
natraj_archu
Posts: 9
Registered: ‎01-13-2011
0

spartan6 fpga Jtag connection issue

Hi..

 

 Every body i have trouble in connecting the Jtag connector with my new board...i used the following signal

 

TCK,TDI,TDO,TMS,VREF(3.3V),GND .....i have trouble in TDO ...is always 1 (i am using Platform cable II usb) ..

 

i checked with scope TDO always high....power supply to spartan6(1.8V,2.5V,1.2V) all ok..

 

please help me

 

Thankyou

Expert Contributor
gszakacs
Posts: 5,267
Registered: ‎08-14-2007
0

Re: spartan6 fpga Jtag connection issue

Since it's a new design, you should first double check that the pinout is correct.  Also

there may be a pullup resistor on TDO in the JTAG cable, so check to see if TDO

is still high with the cable disconnected.  If not, then it is high-Z or (more likely) not

connected to the FPGA TDO pin.

 

Also because the TDO pin may normally transmit a one at startup, you need to check that

TDI, TCK and TMS are all properly connected to the FPGA.  Any one of these could cause

the issue you are seeing.

 

HTH,

Gabor

-- Gabor
Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009
0

Re: spartan6 fpga Jtag connection issue

[ Edited ]

For an unconfigured Spartan-6 device, no external pullup resistors are needed on the JTAG pins.  The JTAG pins are internally pulled up to VCCAUX when the device is not configured.

 

Platform Cable connector (header) connections as follows should be completely sufficient:

Spartan 6  header pin

TDI           10

TDO            8

TCK            6

TMS            4

VCCAUX         2  (note:  VCCAUX, not 3.3V if VCCAUX is 2.5V)

GND       1,3,5,7,9,11 (probably only 1 pin connection to GND is enough)

If the FPGA is already configured, and the FPGA's JTAG port pins are not "reserved" as dedicated JTAG, then user IO functions may very well interfere with the JTAG functions.

 

- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Visitor
natraj_archu
Posts: 9
Registered: ‎01-13-2011
0

Re: spartan6 fpga Jtag connection issue

hi..

 

 Still same problem(my new board-spartan6 fpga)....this is the message i got everytime i initialize Jtag chain

 

ERROR:iMPACT - A problem may exist in the hardware configuration. Check that the cable, scan chain, and power connections are intact, that the specified scan chain configuration matches the actual hardware, and that the power supply is adequate and delivering the correct voltage.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.

 

i checked  connection every thing is ok.....now am clueless about that jtage connection... i am using 7 pin jtag connector and  my board power supply LDO  ampere capacity(1.2V(1A), 1.8v(800mA) ,2.5V(800mA),3.3V(800mA))

is there any power related problem?

 

my jtag signal  TCK,TMS,TDI,TDO,Vref(3.3V),GND....i checked with Scope TDO signal always high...all other signal seems to be ok

 

This signal Enough to connect  my board? or what i have to do with PROGRAM AND INIT pin of Spartan6 fpga  my design

INIT left open and PROGRAM PIN pull down...

 

 

 

 

 

 

 

 

 

Expert Contributor
gszakacs
Posts: 5,267
Registered: ‎08-14-2007
0

Re: spartan6 fpga Jtag connection issue

PROGRAM is an active low input.  It should be pulled up.

INIT is also active low and should be pulled up.

 

This is all shown in the Configuration User Guide.  Note that the device data sheet

does not have all of the information you need to use the device.  You need to look

through the appropriate user guides.  These are available here:

 

Spartan 6 Documentation

 

-- Gabor

-- Gabor
Visitor
natraj_archu
Posts: 9
Registered: ‎01-13-2011
0

Re: spartan6 fpga Jtag connection issue

hi..Thankyou for reply

 

Yes i connected the Prog pin Pull up.. (in my new board design)

 

Regarding Mode Setting M0 and M1

 

in my user guide they told 00,01, only(Master Byte  Bpi,  External spi)  what is Master Jtag Mode? 

 

i searched that sp601 user guid they used only Mini Usb based Jtag connection...only

 

i need Platform Cable USB jtag   i can't move further in my project work without this

 

Please let me know

 

 

Thankyou

Xilinx Employee
mcgett
Posts: 3,513
Registered: ‎01-03-2008
0

Re: spartan6 fpga Jtag connection issue

Ok, you fixed the PROGRAM_B pin, but what about the INIT_B pin?

 

 

------------------------------------------------------------------
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Visitor
natraj_archu
Posts: 9
Registered: ‎01-13-2011
0

Re: spartan6 fpga Jtag connection issue

hi..

 

 I can't change anything Init pin because i left open...i mean that pin is not connected anywhere...in my hardware is that trouble?

 

Thankyou

Xilinx Employee
mcgett
Posts: 3,513
Registered: ‎01-03-2008
0

Re: spartan6 fpga Jtag connection issue

As an earlier posted stated the INIT_B pin should be connected to a PULLUP.

------------------------------------------------------------------
Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
Visitor
natraj_archu
Posts: 9
Registered: ‎01-13-2011
0

Re: spartan6 fpga Jtag connection issue

hi..

 

  Sorry about that i made mistake...

 

 Init_b is floating...in my design

 

i guess this is the problem...becasue Init_B as input before Mode select pin sampling right?

 

it  initiate the Master Mode CCLK...right?

 

so it seems to be my Spartan6 fpga core not activated right?