3rd Party/Other Boards and Kits

[areyes30]

I am having a problem with binary division in Verilog. I want to get an output that contains the quotient. I will later take care of the location of the decima. The following code works perfectly, and I can display the output, which matches exactly what I am looking for.

assign dividend = 48'h800000000000; 

assign quotient = dividend / 24'ha00000;

However, when I try a slightly different approach, as seen below, I get the following error.

assign dividend = 48'h800000000000;  
assign quotient = dividend / {1'b1, in2[22:0]};

The error is:

ERROR:Xst:870 - "fp_arith.v" line 293: Can not simplify operator DIV.

I tried searching for this error online and found little information. Would someone please help me figure out why the first case works, but the second one will not. Thank you in advance.

[ywu]

You may get faster response if you posted your question on the synthesis board.

The division support is very limited. In fact, XST UG states that it only supports when divisor is power of 2 (see snapshot below). You may want to use the "Divider Generator" from CoreGen. For CoreGen 11.x, you will need to apply a patch available from  http://www.xilinx.com/support/answers/33993.htm