7 Series FPGAs

[eteam00]

For the FPGA families up through S/V-6, the VCCAUX supply is used for PLLs which are sensitive to noise.  There are advisories here and there to provide a separate supply and power plane island for VCCAUX.  Often the VCCAUX supply voltage is the same as a VCCO supply voltage, so creating a new VCCAUX-only island is in addition to the VCCINT, VCCO (logic), and VCCO (DRAM) islands already needed.  Depending on design rules and board stack-up and device pinouts, this is *not* easy to implement.

In the wild hope that Gen 7 device final package designs are not frozen and completely tooled and ordered, here is a suggestion.

Separate the supply for PLL (and A/D converter) circuitry which is noise sensitive from the VCCAUX supply with an inductor (or several inductors, for multiple isolated islands) for isolation.  Steal some package pins from the VCCAUX supply and re-allocate them to the noise-isolated island(s) on the package.  Instead of VCCAUX alone, we now have VCCAUX, VCCAUXPLL, and VCCAUXADC supplies and package pins.

Decoupling caps on the circuit board for the VCCAUXPLL and VCCAUXADC pins complete the noise filter, combined with the on-package inductor(s).  The VCCAUXPLL and VCCAUXADC pins serve only two purposes:

1.  decoupling -- they don't need to be connected to each other, just to a decoupling cap for each pin.  This reduces the circuit board layout complexity somewhat compared to dedicating an additional supply island.

2.  if noise isolation is not needed or desired, or if circuit board layout is too tight to afford carving out the VCCAUXPLL and VCCAUXADC pins, these pins are connected to VCCAUX supply in the circuit board layout.

This has two advantages:

1.  By connecting the various VCCAUXxxx pins together, along with VCCO pins using the same supply voltage, circuit board layout is no more complicated than it is for Spartan-6.

2.  By isolating the nois-isolated VCCAUX pins from the board's VCCAUX island, significant noise isolation benefits are realised with a small fraction of the impact or burden on the board layout required by an additional power supply island or plane.

Comments and suggestions are welcome and appreciated.

-- Bob Elkind

[mcgett]

> There are advisories here and there to provide a separate supply and power plane island for VCCAUX

Which advisories are you referring to?  I can't recall seeing this anywhere.

[eteam00]

Which advisories are you referring to?  I can't recall seeing this anywhere.

Well, I'm digging through my notes.  First one is UG393 v1.2, Power Supply Consolidation section on page 31.

To design for reduced noise-levels on the VCCAUX supply, separate supplies should be provided for VCCAUX and any of the VCCO voltage rails. However, a common supply to both VCCAUX and VCCO pins (at either 2.5V or 3.3V) is allowed as long as the recommended operating conditions for the VCC inputs are met, as specified in the Spartan-6 FPGA Data Sheet.

Is this vague?  Sure...

Clue #2:  SP605 (but not SP601) has separate VCCAUX and VCCO-2.5V supply.

Hint #3:  UG373 v1.2, Power Supply Consolidation section on page 28

Powering 2.5V VCCO and VCCAUX from a common PCB plane is allowed in Virtex-6 FPGA designs and, except in cases of noise greater than 250 mV peak-to-peak (±5% of the nominal 2.5V), will not degrade device performance.

Then there are the anecdotal reports... (eyes rolling?)

thread 1

I vaguely recall forum posts suggesting that designers should not expect best-in-class performance from on-chip PLLs due to power supply (VCCAUX rail) noise.  That's not much to go on, is it?

That's it.  That's all I can come up with.  Plus my sense of engineering paranoia where PLLs, ADCs, and DACs are comingled with lorry-loads of digital logic.

Are you saying I should switch to decaf and chill, Ed?

-- Bob Elkind

[mcgett · Accepted solution]

Ok, so both UG393 and UG373 (and the thread) say that it is acceptable to share the VCCAUX supply with other supplies, but you need to make sure that the supply stays within the operating range of the VCCAUX (+/-5% in this case).  I suspect that this language is a bit of best practices boiler plate that was added at some point.

The DLLs, DCMs, PLLs, MMCMs, CMTs, etc.. have had a lot of evolution over the years and applying a design guideline from one family or generation to another shouldn't be done.   Internal (die level) regulation of supplies for performance critical blocks has been added to most families in order to minimize the impact of external noise sources.   One area where this can't be done is on the global clock trees due to the vastness of the networks and these are supplied by VCCINT.

Keep your supplies quiet and within tolerance.  If there was a definitive need for a quiet supply then this would be broken out as its own pin on the package and separated from other internal noise sources within the package.

Other notes: 

The SP605 (and nearly every other Xilinx boad) has all FPGA supplies as a individual rails so that power contributions can be precisely measured.  If we were designing this as a "real" board there would be far more supply sharing.

I recently switched to decaf myself and replaced the high daily dose of caffeine laden diet soft drinks with water. Positive health effects, slight negative initial effect on productivity. YMMV :-) 

[eteam00]

I recently switched to decaf myself and replaced the high daily dose of caffeine laden diet soft drinks with water. Positive health effects, slight negative initial effect on productivity. YMMV :-)

I tried to wean myself from coffee (the real stuff, spoon stands up by itself French Roast) for a week.  Even after the caffeine-withdrawal headaches subsided (two days), my week was weak.  Productivity dropped.  I'd like to think I wasn't cranky, but I can't guarantee it.  I have a one pot a day habit.  Blood pressure is 105/80.  YMMV, indeed  :-)

Thanks for the followup post, Ed.  Have a happy Fourth, you and your hard-working colleagues at Xilinx.

-- Bob Elkind