7 Series FPGAs

[chevalier]

Hi folks,

The latest UG586 (7 series FPGAs Memory Interface Solutions, April 24 2012) makes me somewhat confused. On page 133, the third bullet says "The electrical delay of CK/CK# must be at least 150 ps or greater than all DQS/DQS# signals".

Am I right thinking that this doesn't mean anything else than the following:

if (CK delay to each DDR3 device < 150 ps) then

    for each of the DDR3 device, CK delay must be greater than DQS delay

else

    it doesn't matter!

end if;

Thanks for helping!

Claude

[jschmitz]

Here's another way to state the rule.  If the electrical delay from the FPGA to the DQS of the memory is X ps, then the CK delay must be greater than or equal to (X + 150) ps.  So if the delay for a DQS is 800 ps, the CK must be at least 950 ps to that DRAM.  This must be followed for all DQS lines.

[chevalier]

So what you're saying is that the CK delay shall always be at least 150ps longer than any DQS.

The clock is routed from the FPGA through all four DDR3 devices and up to the terminations (ie "fly-by" configuration). This is also the case of the address and control signals. The layout rule for these signals (UG586 7 series FPGAs Memory Interface Solutions, April 24 2012, p. 133, second bullet)  says that "The maximum electrical delay between any address and control signals and the corresponding CK/CK# should be ±25 ps".

The DQS signals are routed from the FPGA to the proper DDR pin (ie point-to-point configuration).

The problem is really with the first DDR3 device (ie the first stop on the fly-by path). That's the one with the shortest CK delay. The other three devices are OK. So in order to meet the requirement I would need to delay the CK and the 26 address and control signals by 75ps (I already have 75ps now). But 75ps is roughly half inch!!! I don't have the room to add 26 x 0.5 inch on my board.

Sorry I need to ask that, but are you 100% sure of your above statement? Or am I getting it wrong? To me, it doesn't mean the same as the UG586 statement at all, so if your statement is exact, please have the documentation updated.

Thanks!

[jschmitz]

Yes, the CK must be 150 ps longer than any DQS.  Yes, that means the address/control bus must also match it.  Yes, we can try to rephrase that statement in the next User Guide.  It was trying to get the point across, but could be improved.

[chevalier]

May I ask what the reason is for this 150ps delay?

Is this a silicon issue that may be resolved in the future or is this something that will afflict the 7 series forever? The write-levelling seems to be able to accomodate large shifts and non-uniformity, ie much larger than 150ps... so this 150 ps delay is really unexpected and hard to understand. Where does it come from?

Thanks!

[yhubert]

I do not understand this guideline neither. A 150ps delay is almost a one-inch extra path! WTF?!!

[chevalier · Accepted solution]

See AR 50086. The requirement will be updated. Basically, all you need is to make sure that for each memory device, CK/CK# arrives after DQS/DQS#. The minimum delay is 0ps and the maximum delay is 250ps. 150ps is a design goal but is not required.

Starting with the MIG v1.6 version of UG586, the guideline will be documented as: "The CK/CK# signals must arrive after DQS/DQS# at each memory device. The recommended value for additional total electrical delay on CK/CK# relative to DQS/DQS# is 150ps or more, but any value greater than 0 ps and less than 250ps is acceptable."

Claude

[jschmitz]

You'll find this already updated in the UG586 on the web:

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_5/ug586_7Series_MIS.pdf