03-21-2012 08:35 AM - edited 03-21-2012 08:50 AM
I'm looking for a reference design (or advice) for Kintex part and a single DDR3 chip. Specifically I've got questions about signal terminations, ODT, and power supplies.
Bank 33 and 34, VCCO = 1.5V
DDR3 chip VDD and VDDQ = 1.5V
I've seen older DDR designs where most of the signals need terminator/pullup resistors to 0.9V. Does the DDR3 on die termination (ODT) eliminate all of these external resistors?
Edit: MIG suggested I use MT41J128M16HA-125, which is a 2Gbit device.
03-21-2012 10:25 AM
Yes, the power supplies need to be 1.5V for DDR3. Depending on your FPGA speed grade and desired memory operating frequency, the Vccaux_io will need to be either 1.8 or 2.0V.
Yes, ODT on the memory side and DCI (HP banks) eliiminates the need for the external resistors on the DQ/DQS/DM pins. However, you'll still need external termination for the address/control lines.
03-21-2012 01:39 PM
You're not using a DIMM, but I still recommend reading Micron's very helpful document TN-41-08 on interfacing to DDR3 DIMMs. Some of it won't be relevant for a discrete DDR3 system, but much of it still will be.
One early decision you'll need to make is the impedance of the traces you use to connect to the DDR3. DDR3 is designed for 40 ohm traces, but you can adapt it to 50 ohm if that suits the rest of your system better. You may need to change the DDR3's reference resistor from 240 ohms to 300 ohms to achieve this.
The DDR3 ODT is highly configurable, TN-41-08 explains some of the options. Use of a simulator like HyperLynx or even spice can help you choose which options to use.
ODT is only present on the data channel pins. For the address and control channel the normal solution is to drive them from the FPGA with a series resistance of say 34 ohms and parallel terminate them to VTT at the DDR3 end with 40 ohm resistors. You *may* be able to reduce this to only source series termination with no parallel termination, but you'd need to check the signal integrity for your particular layout with HyperLynx or similar.
Silicon On Inspiration
$49 Spartan 6 board with 32MB DDR DRAM ?
03-21-2012 01:42 PM
There is a section on termination in the UG586 (http://www.xilinx.com/support/documentation/ip_doc
04-10-2012 08:07 AM
Thanks for the feedback. Based on the user guides and other app notes from Micon, etc. Here's my plan:
Kintex XC7K325T + DDR3 component (MT41J128M16HA-125, 2Gbit, 16-bit data)
This is a DDR3-1066 chip but is run at 400MHz or 800MT/s.
Addr/Control group (A13..A0, BA2..BA0, CSn, RASn, CASn, WEn, ODT) = 50 ohm pullup to VTT.
RSTn, CSn = 4.7k pulldown to GND
Clock (CKp, CKn) = 100 differential termination
Data Group (DQ15..DQ0, DQS, DM) no terminations on the board since ODT is used at both ends.
All traces between the DDR3 and FPGA have Z=50 ohms
ZQ resistor increased to 300 ohms.
VCCAUX_IO = 1.8V
Using two HP banks with VCCO=1.5V and VREF=VTTREF
DCI is used on both HP banks (VRN and VRP resistors = 50 ohms)
VTT and VTTREF voltages are generated with at TI DDR regulator TPS51200DRCT
04-10-2012 11:26 AM
Check your VRN/VRP resistors. If I'm not mistaken, you want 2x the termination value, not 1x, in 7 Series. So I think you need 100 ohm resistors, not 50 ohm.
Don't forget about the trace matching requirements.
CSn will have both a 4.7k to ground and 50 ohm to Vtt? Why?
How about CKE?
I just reviewed a Micron memory datasheet which implies in places that RZQ is variable, yet I came to a sentence which states that RZQ must be 240 ohms. Check with your memory vendor to see if you can adjust RZQ.
04-10-2012 01:26 PM
Oops, typo in my last reply.
CKE = 4.7k to GND
RSTn = 4.7k to GND
CSn = 50 ohm to VTT
Thanks for the heads up on the VRN/VRP resistors and routing tips. I'll look into RZQ values as well.
04-10-2012 02:49 PM
Note that CKE is a high speed signal and must meet DRAM synchronous timing in DDR3. Therefore I recommend you have a normal 50 ohm termination to Vtt on it. It's only used once at initialization in this design and the odds of something going wrong are miniscule, but even so, I'd recommend that you make it as clean as possible.
04-11-2012 07:44 AM - edited 04-11-2012 08:39 AM
I agree, it sounds like CKE is synchonous to the DDR3 clock and thus is a fast signal in need of termination.
In the older versions of UG586 it recommended a 4.7k pulldown for CKE, but I see that in the most recent versions CKE is terminated as a high speed signal. Thanks!