7 Series FPGAs

[pspear@dwavesys.com]

Is it possible to use LVDS and LVCMOS18 in an HR bank? MAP force me to use LVDS_25 in an HR bank which then forces me to use LVCMOS25. Would it work if I just powered the bank with 1.8V anyways?

The documentation indicates that the LVDS and LVDS_25 can be interconnected. That's great but if I cannot interconnect  the LVCMOS25 and LVCMOS18 as well (and I'm guessing not) then it will be really hard to use HR and HP banks together.

My problem is that I have large number of LVDS and LVCMOS signals that all must be compatible but cannot be fit in just the HP or just the HR banks without switching to a larger part. I'd really prefer to avoid that.

Thanks for your help

[mcgett]

The 7 Series has different capabilities in the HR (High Range) and HP (High Performance) banks.   

The HR banks use the LVDS_25 IOSTANDARD and if it as an output the VCCO must be 2.5V.

   HR - LVDS_25 Output - VCCO must be 2.5V

   HR - LVDS_25 Input and DIFF_TERM=TRUE  - VCCO must be 2.5V

   HR - LVDS_25 Input and DIFF_TERM=FALSE - VCCO can be 1.8-3.3V

  HP - LVDS Output - VCCO must be 1.8V

  HP - LVDS Input and DIFF_TERM=TRUE - VCCO must be 1.8V

  HP - LVDS Input and DIFF_TERM=FALSE - VCCO must be 1.8V

[kren]

You can place LVDS inputs (set IOSTANDARD=LVDS_25) with LVCOMS in HR bank.

[nealkendrick]

I have read on some forums that if you use DIFF_TERM = TRUE with LVDS_25 standard on a 3.3V bank, it simply makes the termination stronger (~80 ohms). But those forums were discussing the V5 and S6 lines. Is this also true for a K7 chip? Your use of the word "must" indicates this is potentially not an option with the K7 chip.

[mcgett]

In oder to have the device meet data sheet specifications then you must use a VCCO of 2.5V.