02-21-2012 06:38 AM
I am aware that there were NBTI effects in Virtex 4 and Xilinx released relevant guidelines to manage DCMs in Virtex 4 in light of NBTI effects. Since NBTI affects increase as process geometries shrink and Virtex 7 being a 28 nm device, will Xilinx release some guidelines for managing MMCMs in Virtex 7 in light of NBTI ?
I could not find any documentation or comments related to my question, hence the post.
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02-21-2012 07:04 AM
What you don't know, is that the DCM team (I was one of them) designed a delay line that turned out to be the perfect characterization (test method) for NBTI. Now that we know better, we have designed, and margined all elements so you do not have to be concerned about NBTI.
"We do the hard work, so you don't have to."
There is no issue with NBTI.
And, further, the larger the geometry, the worse the problem. NBTI is an old old problem, one that has been dealt with before, and as you point out, bit us again in V4.
Xilinx San Jose
03-01-2012 08:15 AM
Thanks for that clarification. I was just wondering if that issue has been similarly resolved with V5 and V6 as well. I do see that with V6 MMCMs, an autocalibration block needs to inserted. I am assuming that is because of NBTI. Am I right? Any info that you could share with respect to V5?
03-01-2012 08:35 AM
For any architecture after V4 we have designed for NBTI and have taken the effect into account in the speed files when we can't completely avoid it. The V6 Phase Calibration (notice the name difference as opposed to the V4 name !!) macro is not there because of NBTI. It's there because certain phase shift settings may cause a random MMCM output phase shift after power-up or after Reset. This circuit will issue an additional reset to the MMCM after which the MMCM is guaranteed to have the correct phase.