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Visitor
gamma-mail@mail.ru
Posts: 4
Registered: ‎04-03-2012
0
Accepted Solution

VCCO pins in Unbonded banks

For my device I choose XC7K70T-1FBG676C. In ASCII Package Files i found VCCO_12 and VCCO_32 pins, but there is not such banks.

 

Notes for Table 1-11 in UG475 says:

"VCCO pins in unbonded banks must be connected to the VCCO for that bank for package migration. Do NOT connect unbonded  VCCO pins to different supplies. Without a package migration requirement, VCCO pins in unbonded banks can be tied to a common supply (VCCO or ground)."

 

Can anybody explain for me, what exactly should i do with VCCO_12 and VCCO_32 pins?

If I connect VCCO_12 to 3.3V (as well as other HR banks) and  VCCO_32 to 1.8V (as well as other HP banks)  - it's correct?

If i have no migration plans for the future, can i leave VCCO_12 and VCCO_32 pins unconnected?

Xilinx Employee
ralfk
Posts: 266
Registered: ‎10-11-2007

Re: VCCO pins in Unbonded banks

Yes, bank 12 and 32 Vccos are only for migration from the 70T to the 160T, 325T and 410T in this package. So if you want to do that then connect them as you pointed out. If you are sure that you will never migrate then it's OK to tie them to GND or leave floating in this case because the 70T die does not have banks 12 and 32.

Visitor
gamma-mail@mail.ru
Posts: 4
Registered: ‎04-03-2012
0

Re: VCCO pins in Unbonded banks

Thanks Ralfk!