7 Series FPGAs

[kurgan]

Hello,

I was surprised a little when have seen that FFG1157 and FFG1158 really have 1156 pins!!!

So both packages the same...

New marketing politics? Joke? Mistake? See page 217 UG475 (v1.6).

Next fact...

Virtex 7 Product table haven`t any information about footprint compartibility between 1157 and 1158 packages.

Could you resolve this puzzle, please?

-- Regards,

Victor

"73!"

[ralfk]

We have been doing that for the longest time. It's done to avoid confusion over footprint compatibility. Packages with the same footprint pin count designator in the name  are compatible. If incompatible packages have the same pin count and same type, say FF, and are not footprint compatible then we simply add +1 or more to the pin count designator.

In future families, we will have a new and different scheme since soon the counts may run into each other.

[gszakacs]

Packages with the same footprint pin count designator in the name  are compatible.

Only within the same family.  There was never footprint compatibility between device families

even when they use the same footprint (like the popular FT256 or any of the QFP packages)

and the same core voltage (like Virtex E and Spartan 2E).

Within a family there have traditionally been packages that actually had one more or less

ball to differentiate between compatible devices - usually one for devices with transceivers

and one for devices without transceivers.  Apparently the newer product matrix is getting

denser...

-- Gabor

[eteam00]

>Packages with the same footprint pin count designator in the name  are compatible.

+Only within the same family.

Both answers are vague.

Compatibility in the context of layout footprint means little more than identical ball count, pitch, pin numbering, etc.

Compatibility in the context of board design generally means identical (or subset/superset) pin assignments of GND, PWR, and certain fixed pin functions (JTAG, configuration, etc.).

Designer beware!

-- Bob Elkind

[ralfk]

You are stating the obvious. No compatibility across families. But this was Virtex only.

Migrateable "footprints" require indeed matching pinouts in the framework of sub and supersets. But there is more to it. The packages have to be also electrically migrateable. Think on package caps.

[eteam00]

You are stating the obvious.

Ralf,  to which post or comment are you responding?

No compatibility across families.

Try to think layout designer, not board designer.  The layout designer does not know FPGA, family, manufacturer, or on-package caps (yes, this is a gross oversimplification).  The layout designer cares if the "pad stack" or "layout dolly" for the FFG1157 matches the "dolly" for the FFG1158 or the NotFreeScalePowerMops SOC CPU 1156BGA.  In other words, the "dolly" library for the layout editor is a matter of little more than mechanical/physical (and not electrical) attributes.

It is the schematic editor library which cares about both mechanical/physical and electrical attributes.

It is the schematic-level board designer who cares about footprints with migration paths.

These are three different levels and contexts of "compatibility".

-- Bob Elkind