12-22-2011 09:52 AM
I am doing some test designs in 7 series parts (7K480T, 7VX485T) with ISE 13.3. In PlanAhead, I noticed that the BRAM and DSP sites are now labeled ..._L and ..._R, presumably "left" and "right". As far as I can tell, this is a new distinction since Virtex-6.
What is the significance of this? Is there any difference between a BRAM_L and a BRAM_R site? Utter speculation: perhaps the difference is in asymmetric interconnect resources to the adjacent LUT fabric?
Is the _L vs _R distinction something an expert Xilinx designer ought to consider to achieve best quality of results? In older devices I have not noticed a significant performance improvement through placing logic immediately to the left vs. right of a BRAM.
(If there is no difference, why the different labels? "The difference that makes no difference is no difference.")
Solved! Go to Solution.
12-22-2011 09:56 AM
7 series has a new architecture which places resources to the left and right of the interconnect.
Is it better? Can it be better (routed)?
We will leave that up to the tools to determine. Since there is no "FPGA Theory" there is no way to know, other than to try.
Now, we wouldn't have made this change, unless it gave us advantages. But with every new technology node, there are changes. Is this a "big change?" I do not thinks so.
Xilinx San Jose
12-22-2011 10:05 AM - edited 12-22-2011 10:10 AM
Thank you very much for the instant response, Austin. Your response is helpful, albeit not prescriptive! I will have to spend some quality time with some test circuits and FPGA Editor.
Gray Research LLC
12-22-2011 11:25 AM
I don't know that you should particularly care about this. But to be clear:
In previous Virtex architectures, the Interconnect block(s) was always to the left of Logic blocks thus alternating blocks and interconnect. The IC would present its inputs and outputs on its right edge for the Logic blocks. Thus, Interconnect blocks would always alternate with Logic blocks in the architecture. In 7-series, a pair of interconnect blocks always come together, in a back-to-back fashion. We call that B2B interconnect. One of them presents its inputs and outputs on its right edge for a logic block on its right. The other presents its inputs and outputs on its left edge for a logic block on its left. So esentially you have interconnect to both sides of a block. For CLBs there are 2 Interconnect tiles next to each other and two logic tiles next to each other. Similarly, the global vertical leaf clocks from the HCLK are shared between the pair of Interconnects that form a B2B INT.
The main reason for this is savings in metal and area savings.
Hope this answers your question.
12-22-2011 12:03 PM
Perhaps I wasn't entirely clear. For the BRAM and DSP fabric interconnect is one sided and is placed on either the left or right side depending on the particular location. So CLBs are back-to-back or back-to-back with a DSP or back-to-back with a BRAM withe interconnect on either side.
12-22-2011 05:55 PM - edited 12-22-2011 05:57 PM
Thank you Ralf, for the additional background. I am all for less area! Viewing the logical device layout in FPGA Editor makes this very easy to visualize.
For curiosity's sake, I just did a couple of simple tests, involving a simple 15b address counter driving a 32Kx1b BRAM, the LUTs/FFs constrained to be immediately to the left or immediately to the right of the BRAM. I made absurb artificially tight timing constraints (clk period 1.2 ns, ignoring component switching limits, just focused on LUT-BRAM net routing delays).
I found it made very little difference whether the LUTs driving the BRAM addresses were on the left or right of the particular BRAM_L, just some tens of ps or so, and that is easily in the noise of the particular routes chosen.
So in conclusion I am not going to let the BRAM_L or _R "tail" wag the dog of where the LUTs fall vs. the BRAMs in my floorplanned designs.
Gray Research LLC