Archived ISE issues

[vanmierlo]

Hi,

I've created a dual ported RAM with the Core Generator (Block Memory Generator 2.8) and this seemed to work (though it only reads 'UUUU' in the simulator). But since I've added a .COE file for initialization of the RAM I can no longer simulate my design with the Xilinx ISE Simulator. I get an error saying:

Cannot open file 'coregen_wavelet_ram.mif'

The file is properly generated by coregen, but the simulator seems unable to find it.

I've already manually downloaded en started the IP Update 3 (allthough it should have been installed already) but to no avail.

Is anyone else experiencing the same problem and is there a known solution?

Btw. Before the error I also get two peculiar warnings:

WARNING:HDLCompiler:321 - "K:/IP3_K.12/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V2_7.vhd" Line 428. Comparison between unequal length arrays always returns FALSE
WARNING:HDLCompiler:321 - "K:/IP3_K.12/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V2_7.vhd" Line 682. Comparison between unequal length arrays always returns FALSE

What is this about and why does it mention V2_7 when I have Block Memory Generator 2.8 installed?

All help is appreciated,

Maarten Brock

[vanmierlo]

Update: I've created a new coregen ram with version 2.8 and now it shows V2_8 as expected. Still the problem remains that it cannot find the .mif file.

[000xjy000]

Hi, I've also experienced the "mif" problem, when i copy the .mif file which is generated by CoreGen to the ISE project directory, it seems to work well. 

So you please try it

thks