Archived ISE issues

[cbeighley]

I've gotten this same error when under Synthesis/Process Properties/Xilinx Specific Options the box Add I/O Buffers is unchecked. XST seems to remove signals unnecessarily if this is not checked.

[christovt]

ALSO CONSIDER THIS SILLY MISTAKE.

I vhdl file I have declared busses, for example C  : in std_logic_vector(11 downto 0);

and in the UCF I declared 

NET "C0"  LOC = "P21"; 

NET "C1"  LOC = "P22"; ........ THIS IS OF COURSE WRONG. With this I get failure Error: ConstraintSystem:59

The declaration in UCF should be 

NET "C<0>"  LOC = "P21"; 

NET "C<1>"  LOC = "P22"; ........ 

CvT

[amer_c]

I have seen this error several times. It happened to me when I have had to force quit Xilinx. I did as mentioned above and no luck ... Finally, I changed the active top module (by selecting another file .sch in my case) and cleaned up the project files. I reverted to the top module (my original schematic as before) and the error disappeared after. I use Xilinx v10.1, but could be helpful for other versions as well).

En français: J'ai eu ce genre d'erreur à quelques reprises après avoir fermé Xilinx de façon brusque. J'ai essayé les consignes ci-haut sans succès. Éventuellement, j'ai dû modifier mon TOP MODULE (le schématique principal), j'ai nettoyé les fichiers de projet PROJECT -> CLEANUP PROJECT FILES et j'ai remis mon schématique de TOP MODULE comme avant. Voilà cela fonctionne. J'ai Xilinx v10.1, ceci pourrait être uitle pour les versions rcents également.

Salutations ;)