Error message : Buffers of the same direction cannot be placed in series.

sylee420 · ‎02-20-2008

When I compiling DCM module, I have the following error messages. I don't understand. What is the cause of this problem?

If I have connnected two DCM modules in series, BUFFER conflicts occurs. How to fix this problem?

ERROR:NgdBuild:770 - IBUFG 'dll_int/CLKFB_IBUFG_INST' and BUFG 'bufg_clk_out' on
   net 'fpga_clk_out_OBUF' are lined up in series. Buffers of the same direction
   cannot be placed in series.
ERROR:NgdBuild:462 - input pad net 'fpga_clk_out_OBUF' drives multiple buffers:
     pin I on block dll_int/CLKFB_IBUFG_INST with type IBUFG,
     pin I on block fpga_clk_out_OBUF with type OBUF
ERROR:NgdBuild:924 - input pad net 'fpga_clk_out_OBUF' is driving non-buffer
   primitives:
     pin O on block bufg_clk_out with type BUFG
ERROR:NgdBuild:947 - input pad net 'fpga_clk_out_OBUF' is driving non-input
   buffer(s):
     pin O on block bufg_clk_out with type BUFG
ERROR:NgdBuild:770 - IBUFG 'dll_ext/CLKFB_IBUFG_INST' and BUFG
   'ibufg_sys_clk_fb' on net 'sys_clk_fb' are lined up in series. Buffers of the
   same direction cannot be placed in series.
ERROR:NgdBuild:462 - input pad net 'sys_clk_fb' drives multiple buffers:
     pin I on block dll_ext/CLKFB_IBUFG_INST with type IBUFG,
     pin I on block dll_int/CLKIN_IBUFG_INST with type IBUFG
ERROR:NgdBuild:924 - input pad net 'sys_clk_fb' is driving non-buffer
   primitives:
     pin O on block ibufg_sys_clk_fb with type BUFG
ERROR:NgdBuild:770 - IBUFG 'dll_ext/CLKIN_IBUFG_INST' and BUFG 'ibufg_sys_clk'
   on net 'sys_clk' are lined up in series. Buffers of the same direction cannot
   be placed in series.
ERROR:NgdBuild:462 - input pad net 'sys_clk' drives multiple buffers:
     pin I on block dll_ext/CLKIN_IBUFG_INST with type IBUFG,
     pin I on block LAC1_not00001_INV_0 with type INV
ERROR:NgdBuild:924 - input pad net 'sys_clk' is driving non-buffer primitives:
     pin D on block LAC4 with type FD,
     pin O on block ibufg_sys_clk with type BUFG

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 10
Number of warnings: 0

sdabrase · ‎10-15-2008

This is a peculiar problem with few of Xilinx architecture. I am trying to get one Spartan3 design onto Virtex2P and facing the same problem for a inout differential signal. But in your case its DCM so no need to worry. There are cascaded DCMs avilable under coregen, use them rather than manually connecting. This should solve your problem.

nipbor · ‎04-15-2008

Hi,

I have a similar problem, but this time I am connecting two DCMs (both generated using Xilnix's IP coregen) in PARALLEL. Therefore both clock inputs of the DCMs are connected to the clock input pad.

An NgdBuild 462 error is displayed. The error states that "input pad net clock drives multiple buffers

pin 1 on block Inst_DCM_5/CLKIN_IBUFG_INST with type IBUFG

pin 1 on block Inst_DCM_x2/CLKIN_IBUFG_INST with type IBUFG "

I tried to disable the ADD I/O BUFFERS from the Xilinx Specific Options properties but it still did not work.

I am using ISE 9.2i

Any ideas please?

Thanks in advance.

Cheers

ywu · ‎11-28-2007

It's mostly likely that when you generated the DCMs, you selected "External" for "CLKIN Source" and the tool then inserted the global clock input buffer (IBUFG) in the generated DCM code for the both DCMs. The error message basically tells you that a single input can't drive two IBUFGs. You should go back to CoreGen and regenerate the DCM files with "Internal" for "CLKIN" Source.

Cheers,

Jim

Cheers,
Jim