[Help] How can I place and route a submodule of a big design

rickys · ‎08-01-2007

Hi there,

Glad I can be the first one to post in this forum.

I have a question as the title:

I just want to implement a submodule of a big design.
The submodule has more than 1000 pins.
But the target FPGA package is FF668, which has less user pins.
How can I run place and route of this submodule?

Thank you in advance.

blackkeymaestro · ‎08-01-2007

Hello,

You can try connecting your clock lines and input lines, but leave the output nets dangling. In order to keep the implementation tools from trimming your design, you can then add SAVE NET constraints on the dangling nets. It takes a little trial and error to learn which net requires the constraint, but typically what you want to do is add SAVE NET ('S') constraints to all the nets that wrap around the output logic.

For example, consider a set of 4 input FFs and 2 output FFs. The input of the 2 output FFs are the AND result of a pair of input FFs. This design would require 7 pins, but it can be implemented with 5 (no output pins). By adding 'S' attributes to the nets that wrap around the output FFs, you can keep the output logic and leave their outputs dangling

Give this a try, let me know how it goes.

-Ed

Message Edited by wellion990 on 08-01-2007 07:23 PM

Message Edited by wellion990 on 08-01-2007 07:23 PM

rickys · ‎08-01-2007

Thanks Ed:)

Here's my way:
1. XST --> insert I/O buffer = False
2. NGDBuilder --> Insert I/O Buffer =False
3. Map --> Trim unconnected nets = False

Seems work.

Thank you very much:)

blackkeymaestro · ‎08-01-2007

Glad it worked! I have found in the past that disabling "trim unconnected signals" still allowed some logic to be trimmed by Map. Keep the SAVE NET info handy as it comes in useful when this happens.