10-17-2008 04:37 PM
I hope Systemverilog will be supported in a short time !!!
I 'm tired of the tedious and error-prone port connections and so on in verilog.
The Quartus II of Altera has already supported systemverilog .
Why can't ISE be quick????
I think it will not be too hard for engineers of XST.
Solved! Go to Solution.
10-21-2008 06:42 AM
Yes that is correct. There is a plan to do limited engagement of SystemVerilog support in XST in and update of the 11 series and then have a production release in 12.1
If you are interested in SystemVerilog, please channel the request through your Xilinx FAE.