08-08-2008 02:45 AM
i'm using the last version of xilinx ise webpack : 10.1.02
i'm using the IP code generator for several things such as fifo or multipliers and it works well.
BUT, i'm trying to use the same core generator to generate a pll x2. I'm using a single DCM IP and i fill my settings onto the Xilinx Clocking Wizard. BUT, at the end of the process, only a .xaw file is created. No vhdl file or any other similar file. So how may i use the generated pll in my project ?
thanks in advance for any help
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08-08-2008 03:14 AM
08-08-2008 03:22 AM
thanks for your answer.
The xaw file is added to the project of course, and when i try to view HDL file i've got an empty file and when i try to view HDL instantiation template i've got an error :
Started : "Generate HDL Instantiation Template".
ERROR:HDLCompilers:175 - Source file pllx2.v does not exist
vhdtdtfi:Declaration (Module pllx2) not found.
tdtfi(verilog) completed with errors.
Process "Generate HDL Instantiation Template" failed
08-08-2008 05:28 AM
Check if you already have the .VHD file generated if it does exist and still you see this error clean the generated files and redo the same procedure again?
To clean up the generated files using Project ==> Cleanup generated files.
08-08-2008 06:34 AM - edited 08-08-2008 07:00 AM
You can instantiate a DCM in your design in your VHDL/Verilog code and not use coregen at all.
Take a look at lib.pdf and it will show you the instantiation templates for the DCM.
also there is a XAPP462 which has a couple examples using spartan 3.
There is also a document specifically for Virtex 5 -- virtex5_hdl.pdf
I instantiated a DCM in my design for a Virtex 5 in the verilog language and it is working the code is like this:
This creates a 40 MHz clock from a 62.5 mhz input using verilog language:
//defparam DCM_inst.CLKDV_DIVIDE = 2.0; // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
defparam DCM_inst.CLKFX_DIVIDE = 25; // Can be any interger from 1 to 32
defparam DCM_inst.CLKFX_MULTIPLY = 16; // Can be any integer from 2 to 32
defparam DCM_inst.CLKIN_DIVIDE_BY_2 = "FALSE"; // TRUE/FALSE to enable CLKIN divide by two feature
defparam DCM_inst.CLKIN_PERIOD = 16.0; // Specify period of input clock
defparam DCM_inst.CLKOUT_PHASE_SHIFT = "NONE"; // Specify phase shift of NONE, FIXED or VARIABLE
defparam DCM_inst.CLK_FEEDBACK = "1X"; // Specify clock feedback of NONE, 1X or 2X
defparam DCM_inst.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
defparam DCM_inst.DFS_FREQUENCY_MODE = "LOW"; // HIGH or LOW frequency mode for frequency synthesis
defparam DCM_inst.DLL_FREQUENCY_MODE = "LOW"; // HIGH or LOW frequency mode for DLL
defparam DCM_inst.DUTY_CYCLE_CORRECTION = "TRUE"; // Duty cycle correction, TRUE or FALSE
defparam DCM_inst.FACTORY_JF = 16'hC080; // FACTORY JF Values
defparam DCM_inst.PHASE_SHIFT = 0; // Amount of fixed phase shift from -255 to 255
defparam DCM_inst.STARTUP_WAIT = "FALSE"; // Delay configuration DONE until DCM LOCK, TRUE/FALSE
assign dcm_gnd = 1'b0;
.CLK0(CLK0), // 0 degree DCM CLK ouptput
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D) clock 40 mhz
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(clk_62_5mhz), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(dcm_gnd), // Dynamic phase adjust clock input
.PSEN(dcm_gnd), // Dynamic phase adjust enable input
.PSINCDEC(dcm_gnd), // Dynamic phase adjust increment/decrement
.RST(dcm_gnd) // DCM asynchronous reset input
08-08-2008 07:14 AM
Hi all, thanks for your answers,
golson : that's what i finnally decided to do, because i found no way to generate a vhd file with the coregen. With previous version of weppack ISE (for example 9.1), there was no problem... this is very strange.
anyway, i manage "manually" the DCM and it works for what i want to do.
08-11-2008 08:45 AM
I get exactly the same problem trying to get Coregen to generate the vhdl for a DCM! I've always had to fight the ISE tools to get this working. In 9.1 it would synthesize but you could not view the template - but work it out from the vhdl code.
Cleaning up the project does indeed fix it.
Yes you can infer, but why can't Xiliinx just get the tools working?!
Had to start again with EDK 10.1 and edit the .mpd files to correct the code that IT generated.
02-21-2011 03:05 AM - edited 02-21-2011 03:09 AM
I've the same problem you all are reporting.
I'm using a Virtex II pro (because the board I'm doing a new firmware was an old one) and so I've to use ISE 10.1 (sp3.. the last I've found).
The problem is that MEGACORE GENERATOR (both inside and outside ISE) is bugged and do not generate .vhd.
I've that problem generating DCM but also with other macro (for example gigatransceiver)
Is there any know solution to my problem (I've done a cleanup project files, but without any results) or the only solution to this bug is to forget about coregen and instanziate all from vhdl?
Hope to have missed some obvious fix, cause it couldn't be that a 10.x release of a software still be majoir bugs as this one.