You can instantiate a DCM in your design in your VHDL/Verilog code and not use coregen at all.
Take a look at lib.pdf and it will show you the instantiation templates for the DCM.
also there is a XAPP462 which has a couple examples using spartan 3.
There is also a document specifically for Virtex 5 -- virtex5_hdl.pdf
I instantiated a DCM in my design for a Virtex 5 in the verilog language and it is working the code is like this:
This creates a 40 MHz clock from a 62.5 mhz input using verilog language:
//defparam DCM_inst.CLKDV_DIVIDE = 2.0; // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
defparam DCM_inst.CLKFX_DIVIDE = 25; // Can be any interger from 1 to 32
defparam DCM_inst.CLKFX_MULTIPLY = 16; // Can be any integer from 2 to 32
defparam DCM_inst.CLKIN_DIVIDE_BY_2 = "FALSE"; // TRUE/FALSE to enable CLKIN divide by two feature
defparam DCM_inst.CLKIN_PERIOD = 16.0; // Specify period of input clock
defparam DCM_inst.CLKOUT_PHASE_SHIFT = "NONE"; // Specify phase shift of NONE, FIXED or VARIABLE
defparam DCM_inst.CLK_FEEDBACK = "1X"; // Specify clock feedback of NONE, 1X or 2X
defparam DCM_inst.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
defparam DCM_inst.DFS_FREQUENCY_MODE = "LOW"; // HIGH or LOW frequency mode for frequency synthesis
defparam DCM_inst.DLL_FREQUENCY_MODE = "LOW"; // HIGH or LOW frequency mode for DLL
defparam DCM_inst.DUTY_CYCLE_CORRECTION = "TRUE"; // Duty cycle correction, TRUE or FALSE
defparam DCM_inst.FACTORY_JF = 16'hC080; // FACTORY JF Values
defparam DCM_inst.PHASE_SHIFT = 0; // Amount of fixed phase shift from -255 to 255
defparam DCM_inst.STARTUP_WAIT = "FALSE"; // Delay configuration DONE until DCM LOCK, TRUE/FALSE
BUFG clkbuf1
(
.O (sigclk_40mhz),
.I (CLKFX)
);
BUFG clkbuf2
(
.O (CLKFB),
.I (CLK0)
);
assign dcm_gnd = 1'b0;
DCM DCM_inst
(
.CLK0(CLK0), // 0 degree DCM CLK ouptput
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D) clock 40 mhz
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(clk_62_5mhz), // Clock input (from IBUFG, BUFG or DCM)
.DSSEN(dcm_gnd),
.PSCLK(dcm_gnd), // Dynamic phase adjust clock input
.PSEN(dcm_gnd), // Dynamic phase adjust enable input
.PSINCDEC(dcm_gnd), // Dynamic phase adjust increment/decrement
.RST(dcm_gnd) // DCM asynchronous reset input
);
Message Edited by golson on 08-08-2008 06:59 AM
Message Edited by golson on 08-08-2008 07:00 AM
