08-14-2007 09:43 AM
08-14-2007 01:10 PM
If you can characterize the problem a bit more, I would be glad to help.
Before performing simulation on a "foreign" design, it's helpful to see whether all your source dependencies have been taken care of. You can verify this by making sure that the source hierarchy in the Sources window looks correct. Also, run implementation (at least up to Map) to make sure that your design can synthesize and that all black boxes (cores) can be resolved.
08-14-2007 01:41 PM
08-14-2007 08:40 PM
Running through Translate (NGDBuild) should pull all of your netlists (which that core is using) into one NGD file. When NGDBuild is parsing these netlists it will report on any apparent problems it sees. This will also enable you to do a Post-Translate simulation and everything should work fine. If you try to run a behavioral simulation, then the tools do not know how that core should behave. A behavioral simulation actually uses the simulator to compile the HDL source. ISE Simulator (ISIM) is looking at that netlist as a black box. For most of the cores that are designed to work with Xilinx tools, the cores have a behavioral model. This behavioral model instructs the simulator how that black box will behave. With this core that you are trying to use, you cannot expect to have a behavioral model automatically generated. Try just running with a Post-Translate simulation.