Hi,
I have a really weird problem. My project is composed of a top-level schematic containing multiple blocks (VHDL). The first block in my design is a StrobeDetector which validate a strobe and an address and drives the correct chip select net (to activate the correct VHDL block). Some VHDL blocks have multiple chip select inputs because they have multiple registers.
Something like this:
StobeDetector-CS_00 (output) -----------------------------------> Block 1-Chip Select 0.
StobeDetector-CS_01 (output) -----------------------------------> Block 1-Chip Select 1.
StobeDetector-CS_02 (output) -----------------------------------> Block 2-Chip Select 0.
StobeDetector-CS_03 (output) -----------------------------------> Block 3-Chip Select 0.
...
Everything was working fine. Some days ago, I had to add a chip select to the Block 1 and instead of taking the last CS_xx, I decided to insert the new one at the beginning, giving this:
StobeDetector-CS_00 (output) -----------------------------------> Block 1-Chip Select 0.
StobeDetector-CS_01 (output) -----------------------------------> Block 1-Chip Select 1.
StobeDetector-CS_02 (output) -----------------------------------> Block 1-Chip Select 2.
StobeDetector-CS_03 (output) -----------------------------------> Block 2-Chip Select 0.
StobeDetector-CS_03 (output) -----------------------------------> Block 3-Chip Select 0.
...
From that moment, everything started to go wrong. Using the CS_00 also uses the CS_01 and so on. It's like ISE remembers that Block 1-Chip Select 1 was once linked to Block 1-Chip Select 0, like a net is drawn between the two pins, but not visible. Some kind of corruption. I deleted all the auto-generated files in my project folder, deleted my symbols and recreated them, deleted the nets, etc. Can't fix it. Is it possible that it's a kind of corruption in my project and if yes, where do I find the information on how to refix this. It's a shoot in the dark, but I tried everything and I'm pretty sure everything is sync.
Thanks.
