Archived ISE issues

[zeus17]

Hi,

I have a question on how to define off-chip constraints. I have a Spartan-3 Starter Kit and I'm using the NOR-Flash on the board to read some data in it. The register-to-register path is:

1. Loading the address in a register in the FPGA. This register is directly connected to fpga pads and goes through the board to the Flash address input pins.
2. NOR-Flash asynchronously decodes the address and puts the data onto the data bus. This process is done in 70ns, following the simulation model.
3. After that, data read enters into the FPGA and is being load into one register in the next clock edge.

I'd like to let the timing tool calculate the whole cycle time (maximum frequency). But how can I specify these 70ns Flash access time??

I've seen that there is a constraint called FEEDBACK, that can specify the delay between an output pin going out of the FPGA and an input one, but this is only used in DCM with clock signals... How can I do this??

Thank you!!

[heritage]

Your thinking to much!  The tool will not do this, best way I found is to use modelsim and download the simulation file from which ever chip vendor your flash is.  Do a post place and route simulation.

You don't define off-chip constraints.  Your VHDL must be able to handle it.  Although sometimes you can TIG lines if they are slow or remove the Delay buffers.   

I never constrained FLASH memory before it should just work.  See if you can find and example. 

[zeus17]

Ok,

But if ROM read access time is 70ns, how much do I put for the clock period?? 75ns, 80ns ?? How can I calculate this??  I can't believe that there's no such tool to do this... I have to know the longest path as if the FPGA address, going out off-chip is returning inside again... Simulating the model with timing is not acurate because you are not testing all possible cases. An in-depth analysis of all possible path must be done.


Message Edited by zeus17 on 11-04-2007 11:59 AM