06-19-2008 02:09 PM
I've opened webcase 742701 with details of the issue at hand. In a nutshell, the DCM.v Verilog simulation model has a race that causes it to not implement phase shifts properly. The code sets by non-blocking assignment the "period" and "lock_period" variables at the same time, but uses a continuous assignment that uses "period" as a delay and "lock_period" as a source to generate "lock_period_dly". In Icarus Verilog, NCsim and Verilog XL, the "lock_period_dly" result is not delayed, causing the "lock_period_pulse" to never be generated and thus the "ps_period" (the amount to scale the phase shift) never gets calculated.
So the DCM.v as packaged in 9.1i and 10.1 does not work with at least half the Verilog simulators out there. Unfortunately, I seem unable to convince the owner of WebCase 742701 that this is a problem. I've given him VCD traces from both Icarus Verilog and NCsim that demonstrate the problem, but silence since.
I'm the maintainer of Icarus Verilog and this problem was reported to me by a Xilinx user. Since I also use Xilinx products I have an interest in getting this resolved for the customer. Ideally, I'm looking for a fixed version of the DCM.v that I can pass on to my user, but second best would be a fix that users in general can use. (Third best would be an acknowledgement from technical support that there is a problem and that it will be looked into.)
Perhaps someone in the community has a DCM.v that they fixed themselves that they can share?
The report in the Icarus Verilog issues database is here: <https://sourceforge.net/tracker/index.php?func=de
09-26-2010 04:09 AM
The Possible reasons for DCM not locking might be due to one of the below
- If the input clock is not stable
More Jitter in Input clock
If the DCM has external feedback, the feedback clock will not be present at the DCM CLKFB pin.
GTS is not released during the startup sequence.
when DFS outputs are used and the CLKIN frequency falls outside the specified range
If some problem in VCCAUX voltage like noise spike which takes out acceptable operating range specified in data sheet.
In case when the reset signals of the DCM and PLL are tied together, the second component in the chain will automatically wait for the first to lock before starting it's own locking cycle.
09-26-2010 06:57 AM
Did you even read the thread you are replying to?
Anyhow, the report is 2 years old, my customer (of Icarus Verilog) has long since worked around the issue, and I've long since accepted myself that I was not being taken seriously. Case closed.