Has anyone every noticed after creating a CoreGen block (in this case a DCM) that after the .xaw file is created, you want to instance the DCM in your VHDL so double click on the View HDL Source or Instantiation Template and nothing happens? I say nothing happens, the blue "busy" wheel turns a bit, the mouse pointer flashes to a timer a few times and nothing happens. So right click either of these and it says that the process is still busy. On other IP cores (like FIFOs) it also does not work but if you look in the project directory, there is a .vhd file there that you can rip off.
I get this sometimes when flipping between ModelSim pre and post layout simulations (where the only fix is to "cleanup" the project). Really annoying - after 1hr of trying, I still cannot infer the DCM I made in 5s in CoreGen......
Thanks
