Archived ISE issues

[jaimesotofigueroa]

We have ISE 10.1 web pack, the worst software we have tried everHundreds of bugs, the software gets hanged again and again, and the reasons seems to be trivial, for example just trying to document a schematic diagram of a functional block with some simple drawings made with the usual drawing elements as line, rectangle etc.On trying to synthesize a core, we set the project in schematics again and again, but the core manager resets to vhdl again and again, and after mapping the report sais the core is empty, etc etc. This is crazy.Why did Xilinx Inc discontinue the venerable Foundation 4.2i. We cannot target a Spartan 3E with Foundation 4.2i, why?I am about to loose my client, even when I have been programming Xilinx chips since 1986, when Xilinx was just starting, I have program families 2000, 3000, 4000, Spartan II, and now Spartan 3E, but ISE 10.1 seems to be the final obstacle.

Jaime Soto Figueroa

Santiago de Chile

[johnnyrocketfingers]

I have not seen these issues with ISE 10.1 have you installed the latest service pack SP3, also are you using a  supported OS?

Can yuo confirm you OS and also where the ISE installation is (have no spaces in the path). If the above are all correct, please open a support case.

[jaimesotofigueroa]

John

We have Windows XP professional, and our file paths have no spaces Actually we have compiled several logic and math systems, and we can now see predictable signals in a 4 channel scope. The issue here is that on trying to run the compilation programs, say 

Check Design Rules

SynthesizeImplement Etc A persistent sequence of absurd errors appear, for example   ERROR:DesignEntry:30 - Instance "XLXI_98" referencing symbol   "core_counter_binary_v8_0_28_bits" is out of date.ERROR:DesignEntry:215 - Net "Q(16)" is an illegal name, because there is no   corresponding bit bus for this bit bus member.ERROR:DesignEntry:213 - Net "Q(16)" is an illegal net name, because it is   similar to "Q(15:0)". (For example, if a net is named "A", you cannot name   another net A(0:3).ERROR:DesignEntry:215 - Net "Q(17)" is an illegal name, because there is no   corresponding bit bus for this bit bus member.ERROR:DesignEntry:213 - Net "Q(17)" is an illegal net name, because it is   similar to "Q(15:0)". (For example, if a net is named "A", you cannot name   another net A(0:3).ERROR:DesignEntry:215 - Net "Q(18)" is an illegal name, because there is no   corresponding bit bus for this bit bus member.ERROR:DesignEntry:213 - Net "Q(18)" is an illegal net name, because it is   similar to "Q(15:0)". (For example, if a net is named "A", you cannot name   another net A(0:3).ERROR:DesignEntry:215 - Net "Q(19)" is an illegal name, because there is no   corresponding bit bus for this bit bus member.ERROR:DesignEntry:213 - Net "Q(19)" is an illegal net name, because it is   similar to "Q(15:0)". (For example, if a net is named "A", you cannot name   another net A(0:3).  These errors are really not true, because there is no contradiction with the existence of a bus names Q(15:0) with the existence of other signals Q(16), Q(17), Q(18) and Q(19), because obviously they are part of the bus Q(19:0), this should be recognized automatically, as usual in all CAE software tools. In relation with the core_counter above, it has been regenerated under the conditions of this project, it has been correctly positioned in the source directories, but still it appears to be is out of date, why? One command missing in ISE 10.1 is “UPDATE”, to obligate a core to update, that simple, this command is missing, how to tell, to order some symbol or core to update? I have used Xact, Pal Assembler, Viewlogic View Draw, Xilinx Foundation 4.2i, ORCAD, and many other CAE tools, and never have seen a so disastrous software tools like ISE 10.1 ¿Why did Xilinx discontinue the venerable Foundation 4.2i? Why didn’t they upgrade this venerable software to allow programming Spartan 3E and other new chips? In my modest opinion Xilinx Inc. should revise thoroughly ISE 10.1, a deep brain storming is necessary; the software is very unstable and buggy, please start recognizing these obvious facts. Sincerely 

Jaime Soto Figueroa

Santiago de Chile

[djmds]

I feel your pain.  I too am experiencing numerous problems, from the software periodically ignoring the top module in a design, a schematic page,  and insisting the top module is a lower level VHDL module (the only way to have it recognize the designated top module is to recreate the project from scratch), to being unable to clean-up a project because I do not have write permission to the sub-folders of the current project.  With my existing design; and a test case of 1 input, a buffer, and 1 output; I cannot tie unused IOB's to GND as it attenuates all input signals - it's float or nothing.

Dave

[jaimesotofigueroa]

Hi Dave

Yeah, and add to all this the infamous "fatal ERROR Gui............" for no reasons at all, the ubiquitous "Crash Recovery File", etc etc.

This software obligates to be very suspicious about file paths on updating functional blocks and cores.

For sure we will learn all its intrincacies, but the software will be declared obsolete and no longer supported righ after learning how to use it perfectly, that may be in 2010 or 2011.

Jaime Soto Figueroa

Santiago de Chile

[jaimesotofigueroa · Accepted solution]

Dear Engineers of Xilinx

I want to express my apologies for my offensive words.

Actually all that is necessary to use ISE 10.1 is to study carefully the tutorials and the manuals before beginning a project.

The software is a miracle, a marvel, a master piece.

Thank you Xilinx engineers for your patience and creativity.

Jaime Soto Figueroa

Santiago de Chile

[mike@folsomvillage.com]

Really?!!!?

Which tutorials and manuals did you read?  Because I REALLY want a set of those!

Sadly, I agree that this is the worst software I have ever used.  Unfortunately I am committed due to design constraints.  I love the Xilinx chips, but everything else is the worst.

[jaimesotofigueroa]

Hi Mike All I wanted in my last post was to express my apologies for my offensive words, but actually, the ISE 10.1 software still crashes for no reasons and it is a very dangerous tool to use. One critical issue is the directory paths to libraries, that is attached not to each project but to the software menus in general. This is very dangerous, because of you are unaware, your new project is still attached to an old library. Make sure to redirect to the new project library. Another issue is the infamous “fatal error” on trying to update text on a schematic. This is still a mysterious fault. Another issue is the lack of medium integration libraries like LogiBlox, available in the venerable Aldec Foundation 4.2i. That library had a complete family of programmable bus-wide logic gates, bus multiplexers, ALUs, and other functions that must be re-invented in ISE 10.1. Another dangerous problem of ISE 10.1 is the “project cleaner”, a command to erase a project from bad compilation results. In general I have learned that this command must be avoided, it is best to create a new project including the top level sources. But the most dangerous fault of ISE 10.1 are the infamous “recovery files”. On trying to open an old version of a project, “some times” the recovery files impose over old files thus destroying old buck-up versions, at a point that I am afraid of visiting old versions of my projects. Some times, for no reasons, a project gets unstructured, this is terrible, but for the moment the only way to cope with this is to take snapshots, at the cost of increasing enormously the project size. Yes, all the tutorial documentation is available, but the only real way to learn is the hard way, with my client calling desperately to my office every day. I work long hours 365 days a year. I wonder is Xilinx engineering managers ever read this forum. Best regards Jaime Soto FigueroaSantiago de Chilehttp://www.matharts.cl/

[mike@folsomvillage.com]

I trust that you have applied the patch found here:

http://www.xilinx.com/support/answers/31304.htm

I had to rebuild my project from scratch a lot until I applied this patch - haven't had to do so since.  Why in the world this patch doesn't show up in the update list is beyond me.

I just paid $3500 to move from WebPack to the Foundation version - only because I need the full simulator because my project is too large for the sim lite.  I have already been informed that the Foundation is the exact same stuff - only a lot more expensive.  I haven't received the license yet.

There is a much bigger issue looming.  This feels like one of those cases where the obvious signs of catastrophe are in place and yet the people in control are blind to it.  Eventually, people who have suffered through the ISE nightmare will be afraid to commit to the company for their next project.  I chose Xilinx because I worked with their products ten years ago.  I don't remember having the same issues.  I also like the functionality in the chips; the best possible outcome will be that someone buys the IP and continues to produce the product.

I hope someone does some digging after the crash and writes a good book about this - I, for one, have never seen anything quite like it.

[jaimesotofigueroa]

Hi Mike 

US$ 3500, the best way to escape from the dangers a web pack. I am "visual", and use to design based on schematics. Is there any other graphic tool around to reach the highest integration FPGAs?

Jaime