Archived ISE issues

[mmoo9154]

I'm using ISE 9.1, and it looks like it's using the 1993 version of IEEE.std_logic_1164.  The source control comment indicates it was last changed by Kumar 17-Jan-2003, and it lists a version 4.200 with a modification date of 2-Jan-1992.

The 2006 versions of IEEE.std_logic, IEEE.numeric_std, and IEEE.numeric_bit have been out for over a year.  Up at the IEEE VHDL Analysis and Standardization Group web site (http://www.vhdl.org/vhdl-200x), there is a zip file [1] with libraries for 2006 as well as 1993 compatible compilers.  (I thought I read somewhere that ISE and XST are 2006 compliant.)

Where should I go to get the 2006 libraries for Xilinx/ISE/XST?  Should I just use the source from the IEEE site?  If so, won't that cause trouble if/when Xilinx decides to cut over to the 2006 libraries?

Any suggestions or links (e.g. to relevant knowledge base articles) would be greatly appreciated.

-Mark

[1] http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/vhdl-200x-pkgs_18.zip

[brouhaha]

The 2006 versions of IEEE.std_logic, IEEE.numeric_std, and IEEE.numeric_bit have been out for over a year.

numeric_std and numeric_bit are part of 1076.3-1997.  I looked at the VASG page you referenced, and I don't see any evidence of a newer approved standard, so any files dated 2006 are only drafts, and it is unsurprising that Xilinx doesn't have support for them.

Is there some feature of the 2006 draft that you desperately need?

[duthv]

Hi Mark,

I believe the 2006 standard you are referring to is still not an IEEE standard. This is currently in its final stages and talk is that it will probably be a 2008 standard. It was initially said it would be a 2007 standard, although schedules slipped.

What specific items are you looking for in the standard? Are you asking about the fixed and floating point types? Xilinx XST does support it. We have a ieee_porposed library that we ship with XST in 9.1i that supports the fixed and floating point libraries. Remember not all of this can be successfully synthesized into a FPGA.

The reason we dont say we support it is because it is not a full IEEE standard as yet and we are waiting on that to happen. Additionally as it is not a full standard we have not tested it throughly either and it is based on an order draft. We have seen some issues with it that we plan to address in 11.1 as well. Try it out, although beware that it is probably an Alpha version.

Thanks
Duth

[mmoo9154]

duthv and brouhaha,

Thanks for the quick replies.  The reason I thought VHDL-2006 had been finalized was my (mis)reading of a press release from Accellera from last year[1] along with finding the new libraries up on the VASG website.  It sounded like Accellera had been blessed by the IEEE to complete the VHDL-200x LRM and that they had completed that activity over a year ago.  I hadn't heard any activities that might change the version of the revised standard they had submitted.

The part of the 2006 draft that I desperately would like (as opposed to need) is the much better handling of math operators on std_logic_vectors.  These are the specifc items from the 2006 draft I'm looking for, although there are a large number of improvements that would be nice to have.

The 1997 compliant libraries require ugly movement in and out of signed/unsigned, so most engineers just resort to using the Synopsys "standard" and use the std_logic_signed or std_logic_unsigned libraries without really understanding the ramifications or that these aren't really standards at all.  (And without understanding that when the 200x libraries are finally blessed they will conflict with the std_logic_signed/unsigned definitions.)

Since we're just starting a project, I had hoped we could move towards the 200x (almost) standard.  I did look at the ieee_proposed libraries, but as duthv already said, these only include the fixed and float types.  I don't need either of those for this design.

So, hopefully I've answered the questions you two raised.  Unfortunately, I didn't see an answer to mine.  What should a designer do if they want to use the VASG (apparently draft) libraries?

Would you recommend I just pop these into the ieee folder of the Xilinx install tree?  Should I create an ieee_draft folder?  (Similar to the ieee_proposed approach.)  Or should I incorporate these in some other way?  It would be great if anyone that has actualy gotten a cycle or two to work with the new libraries (using Xilinx/XST) can describe what they did.  Hopefully, *someone* at Xilinx has made a successful pass through the VASG libraries at least once.  ;o)

-MM

[1] http://www.accellera.org/pressroom/2006/AccelleraVHDL100906.pdf

[duthv]

Hi,

I would not recommend just dropping in the libraries, as that will most likley not do much and will very likley fail in the parser. XST comes with pre-compiled libraries, so unless you use it as a user custom library it will not work. That is an option you can use it like you write your own library and that may work. Depending on how those libraries are coded. The chances of having a lot of vendor support for an non-IEEE ratified standard is very low as most people dont want to put something into the tools and then have the standards change on them and go re-do it again. For this request, my suggestion woudl be the following. Try to use it as a custom library and open a case with Xilinx Tech Support and file a Change Request clarifying exactly which aspect you would like to see. Also participate in Accellera and voice your opinions on what you think are higher priority items that the VHDL commitee should be working on.

Thanks
Duth

[mmoo9154]

Duth,

Thanks again for the response.  I just submitted a request to be a member at Accellera.  I thik the highest priority is to get the work they've already done formally accepted by the IEEE so Xilinx (and other tool vendors) can confidently adopt them.  I'll do everything I can to help as an individual.

I'll file a Xilinx change request next.

In the meantime, do you know of anyone there at Xilinx that is active with the VASG (or Accellera)?  If not, I'll ping elsewhere (let me know).  If you do know someone, can you ask them what they did?

My guess after reading the VASG docs in the vhdl-200x-pkgs_18.zip is that we should compile everything into the ieee_proposed library.  I'll do this as a local library, but the change request would be that the entire IEEE proposal be available in ieee_proposed and not just the fixed and float functionality.

Accellera and the VASG have gone to the trouble of creating a VHDL-93 compliant implentation of ieee_proposed.  I'll try to get the 200x version working with ISE, but if it barks, I'll get the '93 version working.  EIther way, I'll post my results here in case anyone else wants to help push the adoption of the new IEEE libraries.

-Mark

[duthv]

HI Mark,

Yes Xilinx is an associate member of the Accellera commitee. I am one of the members of this sub-commitee that drives the VHDL side. We have plans to increase support in the 11.1 timeframe in XST for the new packages and so we will slowly add support for the new constructs in the language. It would be great if you can file the change request against the tools, so that we have customer request information also being tracked on the side. The problem is not the compilation of the new libraries, the problem is usually the lack of the testcases that we have to verify that the new constructs are there correctly. Dave Bishop has done a great job and provided us with a whole list of test cases and if you can provide some too, where you are trying to use a certain construct, then please send that to me us as well. This is very important to ensure that we implement the correct thing.

Thanks
Duth

[kamwad]

Hi Duth,

I have already posted my question in another thread but still struggling with it.

Actually, I am working on "IIR filter implementation on FPGA". I have already doen it in MATLAB/SIMULINK and was able to generate the code as well (Although I am not sure if it's synthesisable). Anyways, I am trying to write the code myself.

I need to do Fixed-point arithematic for my filter coefficients. Now, I came across these Fixed-point packages written by David Bishop on vhdl.org site. But I am struggling to incorporate them in my design. You wrote in this thread that these packages are synthesisable?

The tools I am using are Xilinx ISE 6, Modelsim 5.8c and the target is Spartan-3 xcs200. Do you think I can use these packages for my project? And if you could provide some guidance on how to compile these packages as I don't seem to have a library by the name of IEEE_proposed?

Thanks very much,

Kamran

[duthv]

Hi,

ISE XST only supports these packages in the ISE 9.1 and above version. Although I should add a disclaimer that when David Bishop tried to synthesize with XST he was not as successful. This is why we have not productized it as yet, as the testing has not shown good results. Although we are working on improving this in 11.1 with the new test cases that David  provided us with.

Thanks

Duth

[kamwad]

Hi Duth,

Thanks very much for your reply. I emailed David as well and he has also told me that Xilinx has promised to include them in version 11.1.

But could you please suggest anything else in this regard? All I need is about 4 or 5 addtitions and multiplications but all the arithematic in Fixed-point. I am looking to have 16-bit coefficients and the data as well. I have been suggested a solution from one of your colleagues, to convert the coefficients in fixed-point signed binary form somewhere outside and then use those values in VHDL. But I am still not sure how to generate a synthesisable code. Do I need to use the built-in multipliers? It's Spartan-3 xcs200.

I mean just anything at all that you can suggest to implement an IIR filter on FPGA.

Thanks very much,

Kamran