why the "Total equivalent gate count for design:" is 0?

zansan · ‎03-16-2008

I had build a project "dsha". Input the HDL code. And I click "map report". At last, in the report, "Total equivalent gate count for design:" is 0. why? What is wrong? Part of the report as follow:

Release 8.2.03i Map I.34
Xilinx Mapping Report File for Design 'dsha'

Design Information
------------------
Command Line   : D:\Xilinx\bin\nt\map.exe -ise
D:/Xilinx/vhdl/dsha224/dsha224.ise -intstyle ise -p xqv100-bg256-4 -cm area -pr
b -k 4 -c 100 -tx off -o dsha_map.ncd dsha.ngd dsha.pcf
Target Device : xqv100
Target Package : bg256
Target Speed   : -4
Mapper Version : qvirtex -- $Revision: 1.34.32.1 $
Mapped Date    : Sun Jun 08 15:06:28 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    2
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:             2 out of    180    1%

Total equivalent gate count for design: 0
Additional JTAG gate count for IOBs: 96
Peak Memory Usage: 125 MB

gszakacs · ‎08-14-2007

What is your design supposed to do? The map report shows only two bonded IOB's (2 pins) and no slices used. If all you have is one input and one output wired together you might expect this. Otherwise to need to look at the map report to see what logic has been removed from the design. Logic is usually removed if it does nothing (for example clocked logic that you forgot to drive the clock, so the tools will ground the clock and everything inside becomes constant), or if the output of the logic has no loads (output pins).

-- Gabor

zansan · ‎03-16-2008

I had use all "input" "output" and "signal". but the report show all "input" "output" and "signal" are never used or assigned. I do not know why this happen? Part code as follow:

ENTITY dsha IS

   PORT(start:   IN STD_LOGIC;
             finish: IN STD_LOGIC;
             din:     IN STD_LOGIC_VECTOR(31 downTO 0);
             dln:     IN STD_LOGIC_VECTOR(4 downTO 0);                    ---当finishI=1时,dln=(数据量-1)
             datain: INOUT STD_LOGIC;
     dou:     OUT STD_LOGIC_VECTOR(255 downTO 0);
             hashfin:    OUT STD_LOGIC);
END dsha;

ARCHITECTURE action OF dsha IS

SIGNal datalen: STD_LOGIC_VECTOR(63 downTO 0);
SIGNal mesg:     STD_LOGIC_VECTOR(511 downTO 0);
SIGNal pad:      STD_LOGIC_VECTOR(1 downTO 0);
SIGNal hvalue:   STD_LOGIC_VECTOR(255 downTO 0);
SIGNal msg_num: STD_LOGIC_VECTOR(3 downTO 0);
signal indataout:    STD_LOGIC;
SIGNAL dafi:    STD_LOGIC;

BEGIN

init: PROCESS(start)
BEGIN
datain<='0';
hashfin<='0';
pad<="00";
indataout<='0';
msg_num<="0000";
dafi<='0';
datalen<=CONV_STD_LOGIC_VECTOR(0,64);
hvalue(255 downto 224)<="11000001000001011001111011011000";
hvalue(223 downto 192)<="00110110011111001101010100000111";
hvalue(191 downto 160)<="00110000011100001101110100010111";
hvalue(159 downto 128)<="11110111000011100101100100111001";
hvalue(127 downto 96)<="11111111110000000000101100110001";
hvalue(95 downto 64)<="01101000010110000001010100010001";
hvalue(63 downto 32)<="01100100111110011000111110100111";
hvalue(31 downto 0)<="10111110111110100100111110100100";
END PROCESS init;

indata: PROCESS(finish, datain, pad)
VARIABLE tint1: INTEGER RANGE 0 TO 511;
VARIABLE tint2: INTEGER RANGE 0 TO 1023;
VARIABLE ddatalen: STD_LOGIC_VECTOR(63 downTO 0);
BEGIN

......