I have a bug in my code
that is i m not able to synthesis the code it works fine with model sim and even the syntax check is also correct
plz help in debugging the code
my code is as follows
the code is for calculating one cycle of the ecgwave,,,,,,,
the ecgwave is sampled at the rate of divider......
and the reset switch to repeat the whole process again ......
and the two counters are used to count on time and off time samples ...........
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity test2 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
ecgwave : in STD_LOGIC;
display1 : out STD_LOGIC_VECTOR(7 DOWNTO 0):="00000000");
end test2;
architecture Behavioral of test2 is
type signal_state is(normal,sinusbrad,sinustach,atrialtach,atrialflutter,juncescape,svt,vpb,vt,ventricularflutt,stayidle,svtsinus);
type state_type is(idle,initial ,part1,part2,part3,part4);
signal state123:state_type:=idle ;
signal clk_div:std_logic_vector(20 downto 0):="000000000000000000000";
--signal constart123:integer range 0 to 3000;
--signal counter: integer range 0 to 1000;
--signal counter2: integer range 0 to 2000;
signal state: signal_state:=stayidle;
signal divider: std_logic:='0';
begin
p1:process(clk)
begin
if rising_edge(clk) then clk_div<=clk_div + '1'; end if;
divider<=clk_div(2);
end process p1;
p2:process(divider,rst,ecgwave) --15
variable counter :integer range 0 to 1000;
variable counter2 :integer range 0 to 2000;
variable constart123:integer range 0 to 3000;
begin
case state123 is
when idle =>
if rst'event and rst = '1' then state123<= initial; else state123 <= idle ; end if;
counter:= 0 ;
counter2:= 0 ;
when initial =>
if ecgwave'event and ecgwave ='1' then
state123<= part1;
end if ;
when part1 =>
if divider'event and divider= '1' and ecgwave = '1'then
counter := counter + 1;
state123 <= part1;
else
state123 <= part2;
end if ;
-- end if;
when part2 =>
if divider'event and divider= '1' and ecgwave='0' then
--if ecgwave = '0' then
counter2 := counter2 + 1;
else
state123 <= part3;
end if ;
--end if ;
when part3 =>
constart123 := counter + counter2;
state123 <= part4;
when part4 =>
state123 <= idle;
end case ;
end process p2;
end Behavioral;
