CPLDs

[marimuthup]

We have configured one pin in CPLD as input and this pin is connected to one switch(we can give either 3.3V or 0V) and to one mictor connector. Once we power on the board, through switch we are giving 3.3V to that particular pin. When we probe that in oscilloscope it's 3.3V. But once i connected the LA probe to that mictor(to which the pin is connected) the pin voltage is changing to 2.8V. This is one problem. Similarly we have connected some IO pins to the mictor connector as some test points. These pins are not used in design. In ISE software we have set the KEEPER option. When we probe these pins in mictor it's giving 3.3V, but once i connected the LA probe it's going to 0V. I don't understand why this is happening and all other signals which come from CPU is not effected by LA probe connection. Please let me know why this is happening and what option i have to set for unused pins. I am not able to understand the KEEPER and FLOAT options in the ISE design. Is this only for unused pins or for all input and output pins. Please send some application notes to understand this first.In my design for pins i am using in design i have only defined that either input or output and the pin location. Do i need to mention anything other than this. Please consider this as very urgent issue, we are not able to proceed further in our design.

Thanks in advance...

[ayang]

First, this is not where you open cases for technical support. This is a forum for customers to interact with each other. If you wish to open a case with Xilinx technical support, you need to go here: http://www.xilinx.com/support/clearexpress/websupport.htm

KEEPER and FLOAT refer to internal termination for all of the I/O pins on this family. So inputs, outputs, unused pins, all will have this same method of termination. In CoolRunner-II, the ability was added to have individual pin termination. You do not have to have unused pins set to any particular value - it's setting should have no effect on the issues that you are seeing.

 If you are able to see the signals with an oscilloscope, but not your LA, then it sounds like there is some sort of loading on the LA that is affecting the voltage of a weakly held signal. Perhaps it's not having an impact on the CPU because they are being actively driven? Maybe the CPU has a higher drive strength? I think that you should investigate the LA probe in more depth.