12-05-2010 04:24 PM - edited 12-05-2010 04:26 PM
This quite a beginner's question but I have not been able to figure out how to reset my CPLD (XC95288XL-10-FG256). Researching this function pointed me to set the GSR in one of two ways: Check the option in the Fit properties or specifically define it in the UCF constraints. After trying both way, I still cannot get my device to reset when I press the reset button. Despite checking the "Use Global Set/Reset" check box in the ISE Fit properties, the Fitter report says the following:
** Global Control Resources **
Signal 'Clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
Here is a snippet of my VHDL code:
entity TopLevel is
Clk : in std_logic; -- Clk input 20MHz, 50ns period
PWM_In : in std_logic; -- PWM input active low
Reset : in std_logic; -- CPLD GSR input
Out : out std_logic
Net "Clk" LOC = "M2";
Net "PWM_In" LOC = "D1";
Net "Reset" LOC = "C4" | BUFG = SR;
Net "Out" LOC = "B5";
Am I doing something wrong?
Solved! Go to Solution.
12-07-2010 11:22 AM
A common misconception is that even though the signal is a 'global set/reset' -- it is NOT automatically tied to all registers in the design. You still must connect the reset signal to the registers that you wish to be reset by that pin. The 'global' refers to dedicated routing that is available for this signal. I suspect you may not be making this connection, and that is why it is listed as 'unused' in the report file.