CPLDs

[sparkybg]

Hi,

I am new to FPGA/CPLD world, and trying to do something with a coolrunner 2 device.

Here is the problem:

This single edge block works on both behavioral and post-fit simulation:

reg outclock;

initial
begin
   outclock=1'b0;
end

always @ (posedge clock)
begin
   outclock=~outclock;
end

...but this dual edge block works only on behavioral. On post-fit it gives the "outclock" signal as undefined (x):

reg outclock;

initial
begin
   outclock=1'b0;
end

always @ (posedge clock or negedge clock)
begin
   outclock=~outclock;
end

Why is this happening? Is it simulator issue or my mistake? Should I set some simulation parameters in order for this to work?

This is happening on any clock speed, so I think it is not a timing issue.

[eteam00]

I do not know about CPLDs, but in Xilinx FPGAs there is no such thing as a dual-edge register.  What you are describing does not exist (in Xilinx FPGAs).

The code describes the configuration and use of existing circuits.  The code does not invent new circuits.

The logic you describe suggests you are trying to forward an internal clock to an output pin.  This is a common and well-understood design application, for FPGAs.

Suggest you search existing forum threads for "clock forwarding ODDR".

This is also a FAQ topic in the NEW USERS README, with links.

Here is a recent thread (this morning, in fact) on this topic.

For coolrunner 2 applications, I have very little advice to offer.  Would connecting the "clock" signal directly to an output pin work?  This would be a very simple solution.  Is it too simple?

-- Bob Elkind

[drjohnsmith]

so

on each edge of the clock input, you want the output to change level,

could I ask, is that the same as the output is the same as the input,

[sparkybg]

Forget about the exact code i've written. It is just an example.

Coolrunner 2 has dual edge flip-flops, or at least I understand it this way, looking at the datasheet. It is stated as "clock doubling". I think it has something to do with the architecture of the device - I suspect dual edge flip-flop does not mean for example that a register can be loaded on both edges.

What I am trying to do is an LCD controller with external SRAM. The LCD controller is memory mapped on a RX62N MCU. The LCD controller generates the LCD control signals (hsync,vsync,den,R/G/B), contains 8 pixel FIFO in it, monitors the requests for memory reads and writes from the MCU, and in the mean time keeps the FIFO full of pixel data. All the data and address busses pass thru it also. The RX62 MCU output clock for memory and peripheral interface can be 48Mhz maximum. My idea is to double this clock and perform reads and writes to the SRAM at 96Mhz. This way there will be a larger bandwidth available to the MCU for reading and writing to the SRAM.

Anyway, considering the 8x16fifo, the desogn fits into a 384 cell CoolRunner 2, and this is pretty expensive part, so at the moment I am looking at the Spartan 3AN/Spartan 6 device, and use it's internal PLL for clock doubling, or even tripling.

I am just curious why dual edge  feature does not work on CoolRunner 2 device. Understanding this will help me with my eventual future projects.

As I can understand, Spartan 3AN/Spartan 6 can be configured from internal Flash, so they are nonvolatile devices also. Am I right? I mean, they don't need external config memory to run?

The same design fits flawlessly into the smallest Spartan 3AN device, using part of the block RAM for the FIFO, despite the FIFO is 16 pixels instead of 8. In fact, it can be upto 1024 pixels deep, if I want it to.

[eteam00]

I am looking at the Spartan 3AN/Spartan 6 device, and use it's internal PLL for clock doubling, or even tripling.

Spartan-3AN has on-chip DLL (or DCM), but no PLL.  Spartan-6 has both DLL (DCM) and PLL.

Either DLL (DCM) or PLL can be used for generating a 2x or 3x clock, subject to the datasheet limits.

The original code you posted would not double the clock.  It merely replicates the clock, theoretically.

As I can understand, Spartan 3AN/Spartan 6 can be configured from internal Flash,

Spartan-3AN is a Spartan-3A FPGA with a conventional SPI flash memory incorporated into the FPGA package.  This is a 2-die assembly in a single package.  There is no Spartan-6 version of Spartan-3AN.

so they are nonvolatile devices also. Am I right? I mean, they don't need external config memory to run?

FPGAs are volatile, they must be re-configured at every power-up.  SPI flash memory is non-volatile.  SPI flash memory is external config memory.

-- Bob Elkind

[drjohnsmith]

lots of questions ah mate:

most xilinx fpgas are ram based, 

   loose power and they forget.

      they need to be configured from an external prart.

the AN part, is a bit of a special, 

   having a flash built on to the module,

spartan 6, cheepest is normaly  to use SPI rom chip,

[sparkybg]

Thanks for clearing the FPGA things.

So, I will use a 3AN device for one-chip solution. I am now reading the user guide concerning the clock resources available and the function of DLL's. This appears to be the optimum solution for this project.

The LCD clock will be generated using one DCM (the LCD clock depends on the size of the panel), and the rest of the chip will work using another DCM, doubling the input clock.

Looks perfect. :) ...for now.

Thanks again guys. You have been very helpfull.

[gszakacs · Accepted solution]

Coolrunner II is an exception to the rule for dual-edge flops.  This device should run properly with

the code as written.  What I suspect is happening in simulation is that the clocks negative edge

is too close to the release of GSR, causing an unknown state on outclock.  You might want to

change your test bench so that the clock starts running only after GSR is complete (usually 100 ns

for Verilog simulation).  Somthing like:

initial begin

  clock = 0;

  #110;  // wait for GSR-related activity to settle down

  forever clock = #5 !clock;

end

HTH,

Gabor

[sparkybg]

I will try this out. Thanks.