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Visitor
jasperni
Posts: 4
Registered: ‎11-19-2007

Speed Grade

Can anyone please explain what a speed grade is?
If i tell you my bicycle has a speed grade of 29, you'll probably say something like: "Good for you.", but you wouldn't have a clue about what i just said.
So, can you explain to me how i should see the speed grades.
What do they stand for?
Who defines the speed grades?
Can i compare the speed grades between manufacturers?

I can't seem to be able to find anything about the subject anywhere...
Xilinx Employee
ayang
Posts: 368
Registered: ‎07-30-2007

Re: Speed Grade

There is no consistent definition of a speed grade for all devices. Even for Xilinx, speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

  However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Arthur

Xilinx Employee
barriet
Posts: 2,453
Registered: ‎08-13-2007

Re: Speed Grade

Jasper,
 
As Arthur indicated, it is a relative term that is really dependent on the specific family:
-for CPLDs, it is generally pin-to-pin delays in nanoseconds (lower # = faster)
-for old Xilinx FPGAs (pre-Virtex), lower # was faster
-for modern (Virtex and later) FPGAs, the higher # is faster.
 
The speed grade influences a variety of timing paramters in the FPGA, including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other resources parameters.
 
You really need to consult the specific datasheet to see specific details for timing based on associated speed grades.
 
For example, Virtex-4 speed grades are -10 (slowest), -11, and -12 (fatest)
Virtex-5 spede grades are -1 (slowest), -2, and -3 (fastest)
There is no correlation between these numbers. It is really a relative metric of performance within a specific family.
 
Cheers,
bt
Visitor
jasperni
Posts: 4
Registered: ‎11-19-2007
0

Re: Speed Grade

Thank you very much, guys.
Visitor
sreenivs
Posts: 3
Registered: ‎10-10-2008
0

Re: Speed Grade

Hi bt,

 

   I am trying to understand it as well. Based on Arthur's reply, it (10ns) sounds as a maximum pass thru delay between an input and an output pin. If my understanding is right, it would set a maximum frequency for an FPGA of interest, only if the connections are pass-thru.

 

   Based on my understanding, here is a follow up question: We usually have all kinds of combinational and sequential logic in between input and output pins. When we include all that, what is the significance of the speed grade?

 

Thanks,

Murthy

Xilinx Employee
barriet
Posts: 2,453
Registered: ‎08-13-2007
0

Re: Speed Grade

The pin-to-pin delay description is only valid for CPLDs - as Arthur indicated.

 

FPGAs have significantly more complicated timing models. If you look at the output from speedprint (run from the command line), you'll notice that most of the timing delays of the elements are affected by the speed grade.

 

In general, the only good summary is "faster speedgrades are faster" The specifics will depend on the family, speed grades, your design specifics, etc.

The datasheet can also be useful to understand some of these limitations (e.g. max frequency of the global clock buffer). 

 

The practical application of the speedgrade is very much dependent on your design, your ability to reach timing closure, the amount of time you can spend tuning your design, and the limits imposed by the silicon and the associated speed bins.

 

bt

Visitor
fire_wall
Posts: 1
Registered: ‎09-13-2007
0

Re: Speed Grade

someone can help to sum up a total speed grade list for xilinx devices?

above discussion is really helpful to me, but it will be perfect if the information about spartan3/spartan6/virtex6 family can also be found here:)

Xilinx Employee
barriet
Posts: 2,453
Registered: ‎08-13-2007
0

Re: Speed Grade

All of the information above should generally apply to V6/S3/S6 too.

 

A few notes:

-how a speed grade correlates to actual timing is obviously dependent on the particulars of a specific design, synthesis/implementation options, constraints, placement/routing, etc.

-The tools are timing driven so it can be tough to judge margin in some cases as the tools stop when they meet your goal (e.g. how fast could I really go?)

-you really can't compare speed grades from different families based on the numbers.

-All things, being equal - I would expect a V6 -1 to be slightly faster than a V5 -1. Not because of the #s but because of what I know about the architectures. This may or may not apply to other families. For example, V4 speed grades are -10, 11, and 12. I would expect V5 -1 to be slightly faster than V4 -10.

-There are some exception to the ~15% guideline above. For example, the difference between S6 -2 and -3 is likely twice that. In other words, I would expect a S6 -2 to be slower than a S3 -4, but a S6 -3 may be slightly faster than a S3 -5. But that's just a general guideline.

-speedprint can also be a useful utility - see http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/devref.pdf (Xilinx Command Line Tools User Guide)

 

bt

Xilinx Employee
barriet
Posts: 2,453
Registered: ‎08-13-2007
0

Re: Speed Grade

You should also check the datasheet for the respective family... This is likely the quickest way to see some of the performance differences associated with the speed grade of a particular device.

Regular Contributor
se17828
Posts: 66
Registered: ‎09-02-2010
0

Re: Speed Grade

I guess it will be a pretty dumb question since it has not come up yet, but, is the speed grade a fixed hardware caracteristic or what? I mean, has it to do with the technological procedure used to manufacture de FPGA or is it a configuration parameter that can be changed? The reason I am asking is because i XPS in the project windows i double clicked on "project options -> device: xxxxxx" and changed the speed grade from -3 to -4. I thought that if this was a fixed hardware parameter I sould have received an error when building and downloading the bitstream to the board (spartan 6 sp605 by the way) but nothing happened and the bitstream behaved as expected.

Therefore, I would assume that the speed grade is just a configuration parameter used for something i don't know, but i am not sure that this is the case...

 

Also, how can i change the clock speed for my desing without building a new design from scratch (BSB)? when i runed BSB i fixed the frequency to 66 MHz but now i would like to try a higher one.