CPLDs

[mcrowe@gcdataconcepts.com]

a

I'm not trying to use it as a registered pin.  The VHDL code is

  tp_out <= '0';

Is there a specific report / file which would give a positive indication what the compiler/fitter has done so I can give you a better answer? 

[mcrowe@gcdataconcepts.com]

Update on some  tests I have done today.

I retargeted the code to an eval board for Xc2c256 (the cool 'X' shaped pcb CoolRunner-II Starter Kit).  The long "configuration" time was NOT observed.  The retargeting involved writing a new .ucf file and changing the target device, so I'm fairly confident now that the VHDL/synthesis/fit process is producing what I was expecting (tp_out <='0').

Back to my board.

I looked further at the tp_out pin during this long configuration time.  The period is 1.7 seconds, and it appears to be high-z with a weak pull up during this time.

I powered the device with only the Vccint (Vccio off).  I saw the output rise to 1.8v for approximately 1.7 sec before going to 0V.

I tied TMS, TCK, and TDI to Vccio, there was no change in the startup behavior.

I've read the excellent "XAPP440 Power On Behavior of Xilinx CPLD's".  Lots of great insight into what is going on in the chip! 

Still no success in changing the behavior with the long config time.  Any ideas are welcome! (does that sound too much like begging?)

[austin]

I have asked the question to someone here who should know,

I will post back when I get an answer....

[austin]

"VCCINT rise time is a natural. Stalling in the neighborhood of 1-1.2V where it's open to noise might ne something to look at. Frequently hanging a scope probe on VCCINT makes it go away suggesting insufficient Decoupling."

Try looking at how the Vccint rises....

[ayang]

Mike,

Very curious issue! 

I am assuming that none of the other IOs are working until this ~1.7 delay after power-up, correct ? Or is it just this tp_out that isn't working?

Archive the project and attach it to your next post. I can take a quick look at it to see if there's any hints in the fitter report.

Also are you scoping VccInt at the CPLD pin (as opposed to the output of the regulator - wherever that may be) ?

/Arthur

[mcrowe@gcdataconcepts.com]

---

austin.lesea wrote:

Try looking at how the Vccint rises....

---

Austin
I looked at Vccint rise times. I saw the plateau you referred to

with an external power supply located about 2ft away I observed the following at the chip.

1) a very fast rise to 375mV, <10usec

2) a monotonic rise from there to 1.00V occurring over 1.6msec.

3) a plateau from 1.00V to 1.40V over 1.6msec

4) a rapid rise to 1.8V over 420usec

In the design have a 10uF ceramic about 1in away.  I added a 0.1uF ceramic about 80 mils from the part.  This did not change the 1.7sec configuration time.

[mcrowe@gcdataconcepts.com]

---

ayang wrote:

Mike,

Very curious issue! 

I am assuming that none of the other IOs are working until this ~1.7 delay after power-up, correct ? Or is it just this tp_out that isn't working?

Archive the project and attach it to your next post. I can take a quick look at it to see if there's any hints in the fitter report.

Also are you scoping VccInt at the CPLD pin (as opposed to the output of the regulator - wherever that may be) ?

/Arthur

---

Arthur  the delay is seen on all output pins, not just the tp_out pin.

I am scoping about 50-100mils from the part.  I am using a Very old scope, HP54501. I think it was one of the first digitals out in the early 1980's.  Fast transients on Vccio won't be captured.

See attached for the latest files to build, I am building the x6_1a.jed file, ignore other targets.

[ayang · Accepted solution]

If the delayed output behavior is on all outputs, then it's not anything in the design itself that is the problem. 

I looked at your makefile and it looks like you are using some sort of Digilent software to do the CPLD programming. Is this a Digilent board? I am guessing you are using a Digilent programming cable as well.  Depending on what sort of programming cable that you have, the Xilinx iMPACT programming software may support it. I suggest you try using that to program the CPLD instead of the Digilent tools. My mind is fuzzy on this, but there are additional bits that need to be programmed that aren't in the Jedec file, and if the Digilent tools aren't programming them properly, it could hold off self configuration. 

/Arthur

[mcrowe@gcdataconcepts.com]

I'm out of the office today, but I'll give the Impact software a shot when I get in tomorrow. 

Any special settings needed for the Impact tool to set these special bits?

[ayang]

Nope, these bits will be programmed properly by iMPACT automagically. =)

/Arthur