02-03-2012 04:27 PM
I'm trying to use an XC2C64 as a SPI slave to interface to an MCU. However the compiler complains that I have "too many asychronous sets/resets" in my design -- but I only have 1 as far as I can tell!
I'm using the standard pattern:
process ( clk, reset )
if reset = '0' then
outptx <= ( others => '0');
elsif rising_edge ( clk ) then
What am I doing wrong?
02-03-2012 08:25 PM
The CoolRunner II data sheet seeoms to say that any number of flip-flops in the same
function block can share the same async set or reset terms. So if you really have only
one reset signal, you should not run into this error. Do you have any non-clocked
processes that may have inadvertently created SR latches? If so those are the more
likely culprits. You could look into the fitter report to get more details of the logic created.
If you can't seem to locate the problem, you could post your code to see if someone
else can find it.
02-14-2012 01:51 AM
I am new to the picoblaze and coolrunner II CPLD. Can anyone please explain the implementation of picoblaze on coolrunner II CPLD and also how can we select the perticular coolrunner or how we come to know the particular memory size is if sufficient to implement picoblaze
If possible could you kindly provided with a simple guide or explanation on how the core implemented within the Coolrunner II CPLD. If possible could you suggest any resources that I may look at in order to better understand the working of the PicOBlaze core.
Appreciated if any one give me the solution.
Thanks in advance
02-14-2012 02:41 AM
Please do not open an unrelated discussion topic in an existing forum thread. Instead, please create a new thread (using the "new message" button:
For information on PicoBlaze, including CoolRunner II design, navigate to the PicoBlaze Lounge. You will need a Xilinx website ID (or registration) to "enter" the PicoBlaze Lounge.
-- Bob Elkind
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369
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