11-23-2009 10:24 AM
We have and application that have been running for 5 years. Now suddenly, it started having some problems (spikes in a frequency measurement section). The application was created probably with a very old version. I tried to install that application on my PC and it crash baddly. I was told that this old application don't run on Windows XP. So following the advice, I installed ISE 11. Well surprice, this new version doesn't read the schematic files that I have originally so I have to re-enter them on ISE. Now, the application compiles but with a some warnings. I uploaded it to the physical device and it didn't work. I tried to do some changes and now I the warnings became error saying that this schematic can't be fit on this device. Well....... I did for 5 years, what is wrong now?
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11-24-2009 05:36 AM
I didn't realise that the 9500XL was still suported, Wow.
You say the old application crashed spectacularly on your PC.
I assume that is an old ISE version.
Just how old was it ?
I'm not Xilinx here, but I think most versions of new programs only support one or two versions back.
On an asside, I'm having great fun trying to read a word doc from 2003, and have no success reading m Access data base from the orriginal Access .
Side step this a little.
do you know the old applicatoin runs on say WIndows 98 ?
if so you could install a VM on your PC, I use VMware Player , the free virtulisation tool to allow me to get around such problems.
then at least you can run the orriginal application.
I also use VM to allow one to have multiple versions of ISE on a machine,
that way, assumeing you had the time and software, you could upgrade the original schematics to each version of software to get to the latest.
This brings up a good question that I dont' think has ever been answered, what to do with old archived projects when the tools around them keep changing ?
11-24-2009 06:24 AM
I'm running ISE 4.1i under Windows XP. That's the last version to have the Aldec schematics
bundled in (originally known as "Foundation" and not ISE). If you're having problems with
ISE 11, I would suggest getting the oldest version of ISE you can still run from the "classics"
section of the software downloads.
Version 4.1i is not very different from other even earlier versions. They might also run under
XP with a little fiddling - even though Xilinx doesn't support it. I found that you must have
the Xilinx environment variable set to the installation directory and you must have
%Xilinx%\bin\nt in your path, preferably as early as possible. These older versions are
16-bit applications loosely tied together with the GUI.
11-24-2009 08:39 AM
Thank you guys for your help.
The original version, was 4.2i. That is the version that I couldn't reinstall. Now, i have all the schematics in ISE and it was supouse to work. I was fixing problems since the very beginning. For example, there was a bidirectional bus, created with buffers with enable (tri state) signals. This are not suported on this device. The error instead of telling you that you are using a component that is not suported, says that the signal that is connected to it is not used and is going to be deleted. So the errors are misleading. It took me a lot of time to find that out. Now I now so I did a macro with 8 AND gates so I have an enable signal and I connect all this "buffers" with OR gates to form the bus. Probably this is what the chip doesn't like. Somehow in the old versions, the schematic was converted in the different way. The way ISE does it today, it just doesn't work.
I was following the tutorials but there are screens that are different so there are things that I couldn't do.
I guess the way I did my bidirectional bus (using ANDS and ORS) is not the way to go. Probably I need to try with MUXs. I will keep trying.
I would like to fix this problems with ISE first if possible.
Do you know if there is any other device pin to pin compatible with the XC95288XL that I can use?
Thanks again to everyone.
11-24-2009 10:04 AM
It sounds like this code has never actualy worked then if your having to do mods to make it work !
Ah the days of simple CPLD, where the C is for Complex.
how things change.
Could you try 4.21 in a VM, Assuming you have it that is.
Then I assume the code would compile with no errors,
I seem to remeber that some fpgas actualy did support internal tri states, or maped internal tri states to special mux options. The XL9500XL is not one of them is it ? I wonder if the ISE has forgotten how to map these ? Does ISE support the 9500XL now is a question.
11-25-2009 01:45 PM
This is funny.
I cleaned up the project and I removed all the loc from the pins. Then I started adding the loc by sections and everything was compiling OK. Then I added some more and I got this error Message:
ERROR:Cpld:886 - Function block FB9 was too congested to route successfully.
This occurs due to excessive (>= 50) product term input fanins to this
function block. Consider moving output signals in this function block to less
congested function blocks, buffering output signals that must remain in this
function block, or selecting a larger package.
CS: block property: block_name=/EEA4/EXPANDED_FlattenFull/EEA4 prop.Multi-level logic optimization..General global resource optimization......ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
The funny thing is that the fuction block number 9 are pins from 50 to 59. There is nothing there !!!!!!! This ISE is so bad. Somebody has an idea on how to fix this?
11-26-2009 12:17 AM
you are having fun.
Can we just clarify please.
This HDL code used to fit in this CPLD under an old ISE ?
so step back, what has changed ?
ISE's fitters keep getting improved, for the newer FPGA's. If your using a different ISE, then it is not unknown for older chips that were on the limit not to fit with newer ISE's. Not least errors that were there , and you did not spot are fixed in the ISE.
I don't think this is what you have here.
I think a big step back is needed.
First up , you are changing the code ? Are you changing it for a FPGA or a CPLD.
the 95 series is more like a multiple CPLD than an FPGA. You have to be careful if your used to 4 / 6 input LUT arrangement with lots of FF.
what do we know works ?
Do you have the original code, It's schematic is it not ?
And it's in the older Aldec format I think.
Can we get back to the known working solution.
the ISE and code that we know works.
Fron there we should be able to go forward.
At the moment I feel we have too many unknowns.
11-30-2009 01:40 PM
It does sound like you've gotten over some hurdles of the design migration, but if you did want to try using older tools, you can download them here:
12-02-2009 10:41 AM
My application was created with Xilinx Foundation 4.2i. The schematic files, can't be opened with ISE. For that reason I entered them manually into ISE. I keep having all kind of ridiculous errors like telling me that I have a certain Function block full, when in reallity, I haven't used any of the pins on that particular fuction block.
I have the disc for Foundation 4.2i but I couldn't install it in Windows XP. It crashed badly. I am trying to install a virtual machine with windows NT to see if I can run it.
Thank you for all your help and suggestions.
I wouldn't been much easier with ISE, but obviously, it doesn't support this CPLD even when it says it does.
12-09-2009 11:57 AM
I don't mean to oversimplify, but just because a function block doesn't have any pin utilized doesn't mean that it can't be 'full'.
Take a look at XAPP444, this explains the above situation.
What do you mean when you say ISE doesn't support this CPLD? All versions of ISE support the XC9500XL family.