CPLDs

[rogerk8]

Hello! I am trying to design a special kind of SR F/F symbolically in ECS. The problem seems to be to enable the fitter to understand that the CP-input is not a static one but actually a low-to-high transition sensitive one (i.e hazard controlled). If the circuit is optimized with CP as a static input it is true that all the inputs to the left of CP can be removed as the optimizer in fact does. I have solved this problem by using an available JK F/F instead but I don't like that solution due to proudness. I want to design my special SR F/F in my own descrete way.

I have tried using time constraints in a propagation delay manner but that doesn't help.

Can the optimizer be turned off and will that solve the problem?

I don't know VHDL or Verilog.

Thankful for help!

Kind regards, Roger

PS

The optimizer also complains about some possibility of glitches in the Q_inv feedback loop. I can't see that that is a problem with the exception of the well known fact that SR=11 isn't allowed.

[eteam00]

Roger,

Can you describe in simple text the operation of this special S-R latch?  Or perhaps a truth table might be more straightforward?

This will help us to understand what you are trying to accomplish, and possibly suggest an alternate approach for implementation.

-- Bob Elkind

[rogerk8]

Hi there Bob! Thanks for the fast reply on a saturday night...

You have seen the attachment I recon?

I have 7 inputs:

D_in : Optional syncronous data input (LD controlled)

LD: Syncronous load enable input (SR must equal 00)

S: Syncronous Set input

R: Syncronous Reset input

CP: Clock input (low-to-high transition)

R_inv: Asyncronous Clear input (active low)

P_inv: Asyncronous Preset input (active low)

and 2 outputs:

Q: F/F output

Q_inv: Inverted F/F output

I have attached a truth table and my desperate (but compilable) solution using an already available JK F/F. I could of cource use this and it even gets me the kind of fun feature of SR=11 being allowed (toggling). But I really need my simple descrete version to work. It is too simple to use "IC's" for everything you don't fully understand. At least that is what I think.

Kind regards, Roger

[eteam00]

I can't write VHDL code to save my life, but here is my Verilog translation of what you have described:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date:    12:34:21 05/28/2011 
// Design Name: 
// Module Name:    cpld_forum 
//////////////////////////////////////////////////////////////////////////////////
module cpld_forum(
    input Load,			// enable load of D_in
    input SyncSet,		// synchronous set, overrides Load and SyncReset
    input SyncReset,		// synchronous reset, overrides Load
    input D_in,			// D Input
    input Clk,			// clock
    input AsyncSetN,		// async set, active low
    input AsyncResetN,	        // async reset, active low
    output Q,		        // output
    output wire	QN		// output, inverted
    );

reg flop_input;

//synchronous logic terms
always @(*)
	if	(SyncSet)	flop_input	= 1'b1;	// sync set
	else if	(SyncReset)	flop_input	= 1'b0;	// sync reset
	else if	(Load)		flop_input	= D_in;	// load D_in
	else			flop_input	= Q;	// hold Q

// this is a CPLD flip-flop primitive, with both async set and async reset
FDCPE #( .INIT(1'b0) )   // Initial value of register (1'b0 or 1'b1)
 FDCPE_inst (            // primitive instance named
   .Q   (Q),             // FF output
   .C   (Clk),           // Clock input
   .CE  (1'b1),          // Clock enable input, always enabled
   .CLR (~AsyncResetN),  // Asynchronous clear input
   .D   (flop_input),    // synchronous input
   .PRE (~AsyncSetN)     // Asynchronous set input
);
	
assign	QN	= ~Q;
endmodule

It compiles without errors for XPLA3 target.

-- Bob Elkind

[gszakacs]

I think the problem with your initial design has to do with the CP and inverted CP both going

to the inputs of the two three-input NAND gates.  An optimizer will not cleverly infer that

you're using the inverter as a delay element, so it thinks the output of these gates should

always be high.  I believe you could work around this using a KEEP constraint on each

gate or net, but Bob's solution using the actual registers of the CPLD is much better.

For one thing it's not clear that even in a CPLD with macrocells that a single logic

delay as represented by your CP inverter will be guaranteed to propagate through the

following gates and consistently set or reset the output latch.

-- Gabor

[rogerk8]

I thank you for your effort! You really must like your job!

Here is my solution in a language I can understand, that is basic logical components (I wish I could say gates...).

So you don't really know how a clocked Flip/Flop is implemented on gate basis (or in ECS)? Am I to understand that?

Anyways, I thank you for your reply. I will not disturb you again. At least not on this topic. Later however when my CPU, realized in your magnificent CPLD, is evolving I might get back to you.

Take care!

Kind regards, Roger

[eteam00]

Adding to Gabor's comments...

The gate topology in your original post is reminiscent of 1970s TTL latch/FF structure.  7474 D-FFs were implemented in similar fashion because that was the efficient topology for the bipolar technology of the day.  Keep in mind that the gate-level topology was (and is) only a representation of a device (transistor) level circuit implementation.  You cannot infer that a simple interconnection of NAND and NOR gates, as you have described, must work.  You must understand that there is additional work needed at the device level to make clocked functions work reliably.

Today's technology, either in ECL/CML or CMOS, implements registers and latches with completely different circuit topology.  A gate-level representation of a typical FF would look very much like two 2:1 MUXes, serially connected.

In the case of FPGAs and CPLDs, a successful designer must consider and defer to the structures underlying the various FPGA logic functions.   The logic diagrams and representations are -- for the most part -- oversimplifications of the underlying structures.  In other words, don't try to make a latch or flip-flop using NAND gates in an FPGA or CPLD.  Use the latches and flip-flops which are provided, and let the synthesiser map storage functions to the fundamental storage structures of the target device.

What I did was map your function -- not your gate topology -- to the target device.  Nothing more, nothing less.  Implementing your gate topology in FPGA or CPLD structures might have worked reliably, but just as easily might not.

Remember the old saying, 'when all you have is a hammer, all your problems look like nails' ?

For 74xx 1970s TTL:

When all you have is NAND gates, all your [fill in the blanks]

For FPGAs:

When all you have is FFs and 5-input look-up-tables, all your [fill in the blanks]

-- Bob Elkind

[eteam00]

Roger, this isn't my job.  I don't work for Xilinx.  Nor does Gabor work for Xilinx.

So you don't really know how a clocked Flip/Flop is implemented on gate basis.

I've designed ECL ASICs and FPGAs since the early 1980s, ECL logic systems since the late 1970s, TTL and CMOS logic systems since the early 1980s, and CMOS FPGAs since the late 1980s.  Trust me, I have some understanding of how logic 'gates' are implemented at the silicon (polygon) and device (transistor) level.  I have the grey hair and beard to prove it.

What Gabor and I are trying to convey to you is that the gate-level designs you have developed are based on 'gates' which do not exist in today's FPGAs and CPLDs. The 'gates' you see in the design docs and user guides are representations of  look-up-tables configured to mimic the represented gate

To faithfully realise your designs, you will need to resort to honest-to-goodness 'discrete' SSI logic or 1970s era TTL foundry libraries.

-- Bob Elkind

[rogerk8]

Hi Gabor!

Thank you for your input to my "problem". But how is a clocked F/F implemented in the CPLD then? It has to use a circuitry somewhat like mine with a hazard (due to propagation delay and shown connection) generated glitch, clocking in data at optional clock pulse transition.

Kind regards, Roger

PS

Sending you a fun home made picture of a 74HC00 glitch.

[rogerk8]

Bob, I can't help but laughing at your comments and my ignorance! I will KODO you asap!

Once again, thank you for your reply and interest in my obsolete "problem"! And I am very impressed of your working background!

Take care!

Kind regards, Roger

PS Me, I am just repairing CPU-based (and CPLD-armed) circuit boards all day long. It is actually quite fun because the failures are different all the time and you just have to find them which is the only engineering part of my work. And I miss designing stuff. So now I have decided to try designing a CPU in CPLD technology (instead of wireing a square-meter of descrete gates...).