CPLDs

[rogerk8]

Hi Gabor!

Thank you for your reply. I am especially interested in this statement of yours "So structuring multiple signals to have common AND terms can give you more effective gates from the same array". This is because I really don't know what I am doing macrocell-wise and have a feeling that I will run out of macrocells before I am finnished with designing my primitive 16-bit CPU.

I have however studied the macrocells shown in the data sheet but I still don't even understand how, for instance, a simple isolated AND-function is realised. I do however understand how a PLA works with regard to address in and data out. Just for the fun of it you may view my article http://sv.wikipedia.org/wiki/Digitalteknik#PLA . Once again it is unfortunatelly written in swedish but the picture is handmade and kind of says it all.

Another thing I don't understand is this statement of yours  "If you find you don't need to reset every flip-flop,I would still recommend leaving the reset signal in the design.  If you run out of pins or routing resources, then you can just tie the reset signal inactive in your schematic or HDL" .

It is true that I don't need to reset every flip-flop (most of the registers are don't care), but what do you mean by "leaving the reset signal..."?

Finally, I thank you again for putting so much effort into replying me. I am quite moved because I know so little and often feel that I just ask stupid questions. You have made my week!

Kind regards, Roger Knopp

[eteam00]

Firstly, I kind of appologize for my stupid question regarding all the supply pins. I should have known better.

Yes, you should know better.  I won't bring this up again, if you won't bring it up again.  OK?  :)

But as I recon this can still be a working design approach. I use this asyncronous glitch everyhere in my counters and registers.

So far, this is a paper design, not a circuit board you are designing (and building at great cost).  So feel free to experiment and learn at will.

Another beginners question, what is the difference between a CPLD (Complex Programmable Logic Device, I guess) and a FPGA (Field Programmable Gate Array, I guess)?

I will give you a brief answer which is appropriate (in length and depth) to the user forum context:

In the beginning there were PLDs (also called PALs or GALs).  They were very popular, and grew in popularity.  DEC and IBM both built mini-computers out of PLDs in the 1970s and 1980s.  They grew in size, complexity, and capabilities.

The largest devices evolved into FPGAs, and continue to grow in size and complexity.  They grew dedicated special-purpose functions such as PLLs, RAMs, adders, and multipliers.

The smallest PLDs have remained practically unchanged since the 1980s (e.g. 22V10).

In between the cute little PLDs -- which are seemingly frozen in time -- and the FPGAs -- which grew into million-transistor 800-pin behemoths -- are the Complex PLDs (or CPLDs).  They are not too big, not too small...  just right for some purposes.  They bear resemblances to both FPGAs and cute little PLDs.  In many respects, they resemble simple FPGAs with on-chip configuration flash memory.  The larger CPLDs are as complex (or more capable) than the earliest FPGAs (e.g. Xilinx 3090).

CPLDs lack the special purpose functions of the FPGAs, and internal interconnect is greatly constrained and limited compared to FPGAs.  The basic building blocks of FPGAs are 6-input look-up tables and registers, called CLBs.  The basic building blocks of CPLDs are arcane arrangements of configurable logic gates and a register, called MacroCells.

I'll stop right there.  If you are interested in deeper understanding, there is a wealth of information available at your fingertips.

-- Bob Elkind

[gszakacs]

Not to argue with Bob, but until very recently the term CPLD was only used to describe parts that

had a macrocell architecture similar to the original PALs and GALs consisting of programmable

AND gates feeding either fixed or programmable OR gates (the term PLA was original applied to

the programmable OR version vs. PAL and GAL which described a fixed OR array) all

possibly feeding a single flip-flop, which could possibly be bypassed.

So a CPLD looked pretty much like a few PALs or GALs (or PLAs) thrown together with a new

feature sometimes called a global routing matrix.  Xilinx still uses this definition of CPLD.

The term FPGA describes parts whose internal structure looks like a routable array of "logic

cells" each consisting of a small look-up table (LUT) and one or more flip-flops.  The lok-up

table structure makes some types of logic easier to implement, because it has no limitation

on product terms, but other logic harder to implement (like wide AND gates) because it

has a much smaller number of inputs than a typical PAL macrocell.  Over time FPGA's have

added other features including arithmetic carry chains and embedded hard macros like

multipliers and dual-ported static RAM.

Sometime recently, the company whose name starts with "L" and who brought us the original

GAL (and bought out the original PAL players, too) decided that a small FPGA with on-chip

configuration memory should also be called a CPLD.  If you look at the structure of their

MachXO series, you'll find exactly what everyone used to call an FPGA.  It's small by modern

FPGA standards, but still big enough to be quite useful.

So in essence the line between the FPGA and CPLD has blurred significantly in recent years.

-- Gabor

[gszakacs]

Thank you for your reply. I am especially interested in this statement of yours "So structuring multiple signals to have common AND terms can give you more effective gates from the same array". This is because I really don't know what I am doing macrocell-wise and have a feeling that I will run out of macrocells before I am finnished with designing my primitive 16-bit CPU.

As Clint Eastwood often said, "A man's got to know his limitations."  (and I thought you said you were Swedish,

not "finnish")

I have however studied the macrocells shown in the data sheet but I still don't even understand how, for instance, a simple isolated AND-function is realised. I do however understand how a PLA works with regard to address in and data out. Just for the fun of it you may view my article http://sv.wikipedia.org/wiki/Digitalteknik#PLA . Once again it is unfortunatelly written in swedish but the picture is handmade and kind of says it all.

Another thing I don't understand is this statement of yours  "If you find you don't need to reset every flip-flop,I would still recommend leaving the reset signal in the design.  If you run out of pins or routing resources, then you can just tie the reset signal inactive in your schematic or HDL" .

If your design includes an asynchronous reset, you can drive this input in simulation to make sure

everything is in a known state.  Simulators are designed with multi-state logic that doesn't match

the real world.  They tend to start up assuming everything is "unknown" and therefore usually

get stuck trying to compute the next state, remaining "unknown" forever.  The asynchonous reset

jams everything into a known "1" or "0" state from which the simulation can proceed.

Once you have a working design, you can remove the reset input from the schematic (just the

input pin itself, not the entire net) and connect the net that was driven by the pin to its inactive

state (ground?).  Then the tools will optimise out any logic that might have been required to

implement this reset.

It is true that I don't need to reset every flip-flop (most of the registers are don't care), but what do you mean by "leaving the reset signal..."?

What I meant was not to remove it fom the design.  It's useful for debugging and simulating.

Finally, I thank you again for putting so much effort into replying me. I am quite moved because I know so little and often feel that I just ask stupid questions. You have made my week!

Thanks for giving Bob and me the chance to help.  There are so many people who come to these

forums to be spoon-fed an answer to their problem, and who don't really want to spend the time

to understand the process of designing logic.  It's been a pleasure chatting with you.

-- Gabor

[rogerk8]

Hi Bob!

I had a hard time understanding what you meant in 2b regarding the buffer problem workaround. But now I think I got it! Attaching my interpretation of what you so kindly told me. (The condion OE_A OE_B=11 will never happen).

Thank you! Now I can proceed with building my CPU modules.

By the way, I asked Gabor about the risk of running out of macrocells before I am finished (I actually spelt it finnished, swedish as I am :-) with my primitive 16-bit CPU. I am sorry for not fully putting the effort into understanding and just kind of lazily asking you but if you don't mind you may tell me if my worries are for real.

Kind regards, Roger Knopp

[rogerk8]

Hi again Bob!

In one case I could actually get rid of the wired-OR warnings just by making the marker/net bidirectional. In that case I had two buffers connected output to output as well as to the bus which made a bidirectional definition of the net logical. To be explicit, I made the input pins bidirectional.

In the other case I just had two buffers connected output to output and even there I got rid of the warnings by making them bidirectional. But in this case there are actually no signals coming in, just coming out. So they should be defined as (three-state) outputs in my book.

What do you think? Is this wrong?

Kind regards, Roger Knopp

[eteam00]

If the CPLD tool is happy, and you're happy, then I'm happy.  Your 'workaround' non-wire-OR solution looks good, also.

-- Bob

[rogerk8]

Hi Bob!

I have a final design question. I now wish to design a PROM with a 16-bit wide address bus and a 43-bit wide data bus (my Instruction Register control signals are that many). I have checked the ECS help but found nothing about it. The other day I however got a tip of the day regarding PROM implementation. It said something about me needing to create a cdf-file but I didn't find that especially helpful.

I won't use more than some 200 (out of 65000) adresses so I've been thinking of realizing this PROM/PLA descretely. The only problem is the R_W_inv-signal which is high almost all the time. I could however invert this making the number of  OR-terms handleble. This will be quite tedious work but it will work (if I have enough macrocells left).

Please answer this and I won't disturb you again (with design problems).

Kind regards, Roger

[eteam00]

I have a final design question.

You're no bother, Roger!

I now wish to design a PROM with a 16-bit wide address bus and a 43-bit wide data bus (my Instruction Register control signals are that many). .... I won't use more than some 200 (out of 65000) adresses so I've been thinking of realizing this PROM/PLA descretely.

I'm not an authority on CPLDs, and I'm unaware of internal CPLD RAM or ROM capabilities of the size and scope you describe.  Are you thinking of off-chip memory?  The XCR3128XL device (see the title of your opening post in this thread) has only 128 macrocells.

Maybe I need a project status update, I probably snoozed past one of your posts.

-- Bob Elkind

[rogerk8]

You are too kind, Bob!

No. I hopefully will not have to design a off-chip PROM. But that is indeed a workable solution. I however like to design all CPU related stuff on-chip if this is possible.

I am attaching a PLA solution to my problem. The problem seems to be that there's simply not enough space in ECS to CAD the memory in my preferred way. I have been naive thinking that I could cascade memory segments according to attachment but I will run out of space very soon.

Finally, I am proud to say that I now have a preliminary version of my CPU (disregarding the so important Instruction register memory) available for sale (I almost said :-). But ECS still complains and want some I/O-ports to be wired-OR's. In spite of me making ALL ports bidirectional, this complain still remains I am sorry to say. I don't know why.

Take care!

Kind regards, Roger