CPLDs

[eteam00]

Now I have tried to compile my design for a Spartan3-device (which is the most advanced FPGA my current version of ISE supports).

That's easily fixed by downloading a more current version of the ISE toolset.

ISE now complains about missing symbols (regardless of the fact that "Check Design Rules" worked really nice for all my CPLDs). Do you have any idea why?

Yes, I have several ideas (all guesses), even though I do not use (or contemplate using) the schematic capture tool:

1.  FPGA library is a different library than the CPLD library.

2.  Some CPLD primitives are not part of the FPGA primitives library, even after you switch libraries.

As I am completely unschooled in the ISE FPGA schematic capture flow, I cannot provide detailed solutions.

By the way, what is the difference between a Spartan3 and a Spartan3A which is the only type of FPGAs Xilinx seems to support? (I can currently only choose Spartan3).

For your purposes, the differences are immaterial.  I'm aware of a few differences, but there are none which would either help or hinder your design, with respect to its capabilities.  If you want to use a newer line of FPGAs, you'll want to select Spartan-6 -- after you've installed a newer ISE kit.

So... you have two steps to make in your journey toward boundless abundance of logic-enriched FPGAs:

1.  Install newer ISE kit if interested in Spartan-6

2.  Translate your CPLD design to the point at which it will successfully compile to an FPGA.

By the way, Gabor and Bassman and others are much better able to give you detailed help on the translation/library process.

-- Bob Elkind

[gszakacs]

Roger,

Let's take a quick step backward if you don't mind and revisit the CPLD issues.

1) The fitter was able to place the design in a larger part than you started with.

2) The fitter could not place the design in that (larger) part after you changed the

pin assignments.

3) The fitter coult not place the design in an even larger part using your new

pin assignments.

Why did you decide to change the pin assignments?

Getting back to my previous post, a CPLD is made up of macrocell blocks, each having

a limited number of resources including inputs, outputs, macrocells and product terms.

A larger CPLD in the same family has more of these macrocell blocks, not larger blocks.

So if you place too many resources in one block, for example by adding too may data

pins to the same bank, you overload that particular macrocell block while other blocks

may be nearly empty.  Going to a larger CPLD will not fix this because it still covers those

same pins with a single block.  The larger CPLD will have more blocks, but those

additional blocks cannot route to the pins of another block.  The fitter takes this into

account when it fits the design without pin constraints.  I imagine when it completed,

your data bus was strewn all over the place - because that's the only way it could fit.

Before throwing out this baby with the bathwater, you might want to go back and remove

your pin assignments and give the fitter another shot at it.  When it's done you have the

option to make its pin assignments permanent by back-annotating the design.

If in the meantime you have become totally disenchanted with CPLD's and want to

move on to FPGA's, then I would ask what version of ISE you're running?  If it is

older than 10.1, you should upgrade.  If it is newer than 10.1, you might be forced

to use newer FPGA families than you would like.  With 10.1 you can go back as

far as Spartan 2, which is already end-of-life, but still readily available at DigiKey.

You can get parts in the same 144-pin TQFP your CPLD uses.  Spartan 2 (not 2e)

has 5V tolerant inputs although it runs on 3.3V max supplies.  Spartan 2 (and 2e)

have lots of internal tristate buffers which make the parts hold more logic than

the sum of their LUTs and flip-flops might imply (you can use TBUF-based muxes

for example to save slices).  And you have the satisfaction of using a "retro" FPGA :-)

Still, given the work you've put into this already it seems that another shot at putting

it in a CPLD would make sense.

Regards,

Gabor

[rogerk8]

Hi Gabor!

1) The fitter was able to place the design in a larger part than you started with.

True.

2) The fitter could not place the design in that (larger) part after you changed the

pin assignments.

I did not change the pin assignments, just assigned them (ran Assign Package Pins for the first time).

3) The fitter coult not place the design in an even larger part using your new

pin assignments.

True, but the pin assignments were the same (or approximatelly so).

Why did you decide to change the pin assignments?

As I said above, I did not change them. I however tried to move around the Data Bus and got rid of one warning (out of five) but it did not feel like a working solution. It was then that I thought that there might be something inherently wrong with the Data Bus implementation (because there were only complains about those). And started thinking of FPGA's because my ISE (6.2.01) only contained XCR3512 as largest device and it didn't help going from the second largest to the largest device (quite the same warnings).

I hope you can follow what I mean. I have downloaded version 13.2 but that seems not to be such a good idea if I understand you correctly. A fun thing to mention is that ISE 13.2 is as large as some 5GB (took me three hours to download) while my ISE version (6.2.01) is only some 500MB. What has happened? :-)

I have however not installed it yet. I do not really want to. Think I will get lots of extras which I don't really need. But how may I proceed? I don't understand. Might there still be a way to assign the pins in such a fashion that it will work? Is this what you are telling me? Or should I download ISE 10.1 and go for a Spartan 2 device (which is actually available even in my current ISE version)?

I have put my project on hold pending new ideas from you and myself. My guts tells me that I should proceed with a CPLD solution but the FPGA ROM feature is very attractive.

Thanks for your reply!

Kind regards, Roger

PS

What is back-annotating? That sounds good.

[eteam00]

I have little doubt that with enough attention, you could manage to fit your design into a 512-macrocell CPLD (this is the largest CPLD currently offered by Xilinx).  You will likely be pushing and tugging at both your design and the tools settings to accomplish this.

A fun thing to mention is that ISE 13.2 is as large as some 5GB (took me three hours to download) while my ISE version (6.2.01) is only some 500MB. What has happened? :-)

• more/better documentation
• more device families
• improved/additional features and tools
• more versions of operating systems to support
• Windows software tools and libraries are less mindful of file size
• hard disks -- greatly increased density at the same cost (1000 GB drive is $50 US)

Think I will get lots of extras which I don't really need.

Yes, and many of the extra device libraries and support files can be deleted from your hard disk to recover files space.

Might there still be a way to assign the pins in such a fashion that it will work?

Probably, yes.  No guarantees.  Are you done with your CPU design and ready to spend time squeezing the design into a device?  Or do you have yet more ideas and features to add to your CPU?

Or should I download ISE 10.1 and go for a Spartan 2 device (which is actually available even in my current ISE version)?

I believe the logic simulator (ISIM) in ISE 12.x and 13.x is much better than the logic simulator (if any) in ISE 10.  At some point -- I'm not sure when -- Xilinx switched from 3rd party logic simulator license (ModelSim) to Xilinx-developed ISIM simulator tool.

If you have no interest in designing, fabricating, and assembling a board with your design, then it matters less which device family you choose.  I think Spartan-3 generation devices are supported more completely than Spartan-2 and earlier devices.

The bottom line is (I believe):  Are you done with your invention and ideas phase, or not?

-- Bob Elkind

[gszakacs]

I did not change the pin assignments, just assigned them (ran Assign Package Pins for the first time).

Umm...  Unless something has changed drastically since version 6.2 the fitter must

have made pin assignments to complete the fitting operation.  At least in the newer tool versions

"fitting" means completely mapping the design to the part, which includes making pin assignments.

Note, however that these assignments do not become part of your design until you make them

permanent.

"Back-annotating" means taking the results from the fitter and making them permanent by

adding them to the input design files.

3) The fitter coult not place the design in an even larger part using your new

pin assignments.

True, but the pin assignments were the same (or approximatelly so).

They were the same as the ones that didn't work on the smaller part.  They were not the

same as the pin assignments from the original successful fitting that were never made

permanent (I still contend that you just missed these assignments.  It makes no sense

that "fitting" completes without a pin assignment).  The point I was making is that the

problems stem from too many resources in a macrocell block.  The same pins will still

be within a single macrocell block even in the larger part.  So making the part larger without

fixing the pinout will not help.  This is a partitioning problem.  In the old days you had PALs

or GALs with about 8 macrocells in each device and connected together with board-level

wiring.  A CPLD looks very similar to that circuit board.  If you have run out of product terms

or input pins in one of those PALs or GALs, adding more PALs or GALs to the board

(the equivalent of using a larger CPLD) will only help if you also move some of the output

pins out of the overloaded GAL or PAL.

-- Gabor

[rogerk8]

Hi Gabor & co!

It fits! It actually fits!

After moving the alarming dbus signals around one by one (and totally destroying my beautifully structured pin plan) I got this result:

Considering device XCR3512XL-12-PQ208.
Re-checking device resources ...
...
Synthesizing and Optimizing...
..............................................................................................
...o
.......
Fitting...
.................
...o
java.lang.ClassCastException: org.apache.xalan.res.XSLTErrorResources_sv
 at org.apache.xalan.xslt.Process.main(Unknown Source)
Exception in thread "main"
Design cpu_all4 has been optimized and fit into device XCR3512XL-12-PQ208.
Completed process "Fit".

Now I need only to create a loadable file. I have done it once but it was a long time ago.

Generate Program File went well...

Running Configure Device (iMPACT)...

Selecting Boundary-Scan Mode...

Selecting Automatically connect to cable and identify Boundary-Scan chain...(have no cable here though)

No cable found or likewise is the obvious result.

Then I get a Cable Communication Setup dialog with lots of options. Parallel IV is currently checked but I think our cable is a Platform Cable USB. I will however not change this at this point.

Now I will have to CAD a PCB for the CPLD and peripherals before I can download my fantastic CPU. I am so excited that I'm shaking!

It's a shame though that I could not use my carefully planned pin assignments. But who cares? :-)

And yes Bob, I am finnished with planning the design. I only have one more future option in mind and that is a hard-wired Multiplier and Divider. But that is "only" a software upgrade now that I have assigned all the pins. Using the largest CPLD will also give me maximum space for this.

Thank you guys for all the help!

Kind regards, Roger

PS

When I close ISE, what processes do I have to rerun? Or have I got the programmable file for immediate use somewhere in the project folder?

[rogerk8]

Hi again!

One last question: what is the defined state of an unused pin? Output or Input with pullup? I need to plan ahead somewhat if I choose to be able to implement MUL/DIV (needs a couple more control signals).

Now I will not disturb you for some time. But I intend to supply feedback on my progress. If you don't mind, that is.

Kind regards, Roger

[rogerk8]

Hi!

Here comes some unwanted feedback :smileyhappy:

I am attaching a sample of what I'm now doing. I think it is called microprogramming. I am actually programming the sequence in which each instruction has to pull at the control signals (d0-d42).

It is quite exciting but somewhat difficult. Mostly because the control signals are that many but also the strict sequence in which they have to be programmed. Late in the design I added a signal called IE_D_FA which enables a mux function to use weather the internal D-bus or the ALU-bus where to be connected to the top side of the full adder (FA). This has enabled me to simplify some of the instruction realizations but not all as I hoped. The neccesary CMP-instruction will still, sadly enough, have to use the Stack to work properly. It is actually the only way with my current CPU architecture. I would have needed a internal Temp-register to be able to do it in a more simplfied manner.

Hope you don't find this too boring!

Kind regards, Roger Knopp

PS

I have some trouble getting hold of my precious XCR3512-12PQ208. You can't help me with this, I recon? A single sample would suffice. And I have tried DigiKey but they don't have it in stock.

[eteam00]

I have some trouble getting hold of my precious XCR3512-12PQ208

The XCR3512XL-12PQ208I is in stock at Avnet Express.  They show 37 in hand.

They also have in-hand stock of the -10 and -7 speed grade devices, also in the PQ208 package.

If you're going to build but one board, why not go for the fastest speed grade part?  You aren't obligated to run it at full-on clock frequency, but it's nice to know that you *can*.

-- Bob Elkind

[rogerk8]

Thank you Bob! I really mean that because this is something I should have been able to find out for myself (if I wasn't that lazy that is).

It looks like I actually can buy a single device from Avnet Express (for some $80). This makes me very happy!

I will think about what you are saying about the propagation delay though. If I understand this correctly it is however not required to rerun compilation and so fort if I decide to use a faster device. I could just buy a faster one and turn up the frequency(?)

I'm honored that you think so good of me that you suggest even faster devices. Me, I am humble and only want it to work. Perhaps only at some 100kHz even though I aim at 1MHz.

Take care!

Kind regards, Roger