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Super Contributor
rogerk8
Posts: 165
Registered: ‎05-28-2011
0

Re: Don't PE on me!

Hi Bob!

 

Long time no see!

 

Just want to tell you that I'm skipping the advanced PCB layout procedure and is going to hardwire my CPU. I am expecting a delivery of a "Schmart Board" which eliminates the need for a dedicated circuit board. With the Schmart Board I can continue my journey into a  "Home-Brew CPU on a CPLD". The only problem is that I'm getting more and more excited about my new Tube Amplifier designs. So I don't know what to prioritize. There's many fun projects going on. I am even having a discussion with China about the design of tube transformers. Maybe I will newer row this project ashore but I hope so. My dream is to design a computer from scratch. Take care! Best Regards, Roger

 

PS I have entered the normal CPLD forum.

Super Contributor
rogerk8
Posts: 165
Registered: ‎05-28-2011
0

Re: Don't PE on me!

Hi Bob!

 

My pet project is proceeding however slowly. I am now into placing the actual IC-capsules on a PCB consisting only of islands. I have had problems with finding a sufficient large PCB but I have "invented" plinth-assembly of descrete so called EU-boards (100X160mm). My project is then starting to look like the ship Enterprise :-) I will make use of as many as six of these EU-boards. Five side to side, one half up and one half down around the CPLD-schmart board. At least this is my current plan.

 

My questions to you are two:

 

1) What is the limit for the lenth of a single wire? Right now the maxim length is around one feet(!) and I don't like it (these long wires do however emerge for "slow-rising" PROM data outputs. The fast CPLD output address wires are a bit, but not much, shorter). But the design looks so good now. From above, that is.

 

2) Is there any problem in switching two voltages (3V+5V) on "simultanously" using a 2P switch (I have however a quite large delay in the "weird" reset glitch)? I am thinking of putting the supply outside the "Mother Board". This makes it neat, but is it wise?

 

Take care!

 

Best regards, Roger

PS

I am writing here beacause here I get an e-mail whenever/ifever anyone answers.

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009

Re: Don't PE on me!

1) What is the limit for the lenth of a single wire? Right now the maxim length is around one feet(!) and I don't like it (these long wires do however emerge for "slow-rising" PROM data outputs. The fast CPLD output address wires are a bit, but not much, shorter). But the design looks so good now. From above, that is.

 

There is no theoretical limit for wire length, but signal integrity issues might arise.  Here are some potential problems to keep in mind:

 

  • Without termination resistors, signals can reflect and bounce multiple trips back and forth on each wire.  The longer the wire, the longer the 'settling time' for reflections to diminish.  The net effect is increased propagation delay, which means reduced timing margins.  With a 12-inch (30 cm) wire, the round trip delay for a reflection is roughly 3.6nS.  If you slow down the rise and fall time of the CPLD outputs, this will help hide the reflections in the (slow) rise/fall of the signal.
  • Any signals which are edge-sensitive (clocks, write pulses, strobes, etc.) cannot tolerate excessive reflections or ringing.  Signal edges must be clean, and adequate noise margins must be maintained in the face of undershoot.  If you have signal integrity problems with edge-sensitive signals, there are three simple counter-measures.

1.  Series termination -- a 33-ohm resistor near the source pin will reduce rise/fall time and attenuate reflections.  Do not use series termination with signals which have multiple load pins, this is only for point-to-point single-source single-load signals.

 

2.  Reduce signal drive current or "strength" -- this is essentially the same as series termination, it increases the output impedance of the signal driver.  It also reduces the rise/fall time, which helps moderate signal reflections.

 

3.  With clock signals (or other edge-sensitive signals) with multiple loads, you have one available option:  parallel termination.  In your application, I would suggest 100 ohms (to ground) at the very end of the wire furthest from the driver as a first-trial value.  Some experimentation may be required to optimise the parallel termination resistor value.

 

With any signals with multiple load connections, make sure you wire these pins in a daisy chain rather than radially.  The signal source must be at one end of the daisy chain.  Stubs are allowed, as long as the stub is short (2 inches or less is my guess, in your application).  Keep stubs as short as possible.

 

2) Is there any problem in switching two voltages (3V+5V) on "simultanously" using a 2P switch (I have however a quite large delay in the "weird" reset glitch)? I am thinking of putting the supply outside the "Mother Board". This makes it neat, but is it wise?

 

With a mechanical switch, there is little practical difference between a "delayed" contact make/break and simply turning only one of the supplies on at a time.  This may, or may not, be a problem.  Some devices have a tolerance for inputs driven to an over-voltage level referenced to GND, regardless of supply voltage to the input device.  On the other hand, some devices express input over-voltage tolerance relative to the input device's positive supply voltage.  You will need to check the device datasheets.

 

You may have a problem (it's usually called 'latch-up'), but you are probably OK.

 

Have you considered powering the 3V rail from a regulator which is in turn powered by the 5V rail?  This will give you simultaneous power-up (and power-down) of both supply rails while requiring only a single-pole power switch (for the 5V rail).

 

I haven't given you much in the way of definite answers.  Once in a great long while, I am (barely) overcome with just enough humility to confess that I'm not absolutely confident that I can provide definitive (and correct) answers.

 

Good to hear of your progress, Roger.  Good luck to you!

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Super Contributor
rogerk8
Posts: 165
Registered: ‎05-28-2011
0

Re: Don't PE on me!

Hi Bob!

 

Once again, I am honored that you have put down so much effort into helping me! It makes me feel very happy!

 

I know that long wires isn't good. I will try to keep them short. But this is not easy.

 

I like your termination and/or series resistor usage tip. I will have to think more about this.

 

With regard to your fantastic idea of regulating for 3V after the 5V regulator I am bound to tell you that the minimum difference between in and out of the LM317 I preliminary want to use is 3V (according to Fairchild). So this is unfortunatelly not possible. Moreover, I want to use 3,3V because that is what the "commercial" CPLD seams to like the most (yielding only 1,7V difference). But it is a very good idea. And I have seen it at work (with switched regulators which I don't want to use).

 

I think I will build the supply on the "Mother Board". This makes it possible to turn on the supply using just a single 1P switch (raw DC input will be 9V). I can't imagine that the delay difference between the 7805 and LM317 would do any harm. Especially considering that the POR-pulse is adequatelly delayed.

 

I have done som power calculations and this kind of supply arrangement will actually take the IC's to their limit. This is due to the old PROM's which seam to require some maximum 60mA each. Take this times 7-8 and you have almost half of an Ampere. Half an Amp times 4V equals 2W which I have, since long time ago, calculated is the maximum a "naked" TO220 can withstand.

 

Take care!

 

Best regards, Roger

Super Contributor
rogerk8
Posts: 165
Registered: ‎05-28-2011
0

Re: Don't PE on me!

Hi Bob!

 

Your last message was not available according to Xilinx. Could you perhaps resend it?

 

Best regards, Roger

Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009

never mind...

I deleted the message before you could read it.  It was worth deleting, not worth reading.  Trust me on this...

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Expert Contributor
rcingham
Posts: 2,010
Registered: ‎09-09-2010

Been there, done that, worn out the t-shirt!

[ Edited ]

As a recent graduate about 30 years ago, I co-designed and built a pair of ASIC emulators using discrete logic chips on a group of 3U single Eurocards (same size as yours) in 19" rack. They were wired - no PCB - as were the inter-board-connector connections. Some of the wires must have been about a foot long. No great regard was paid to signal integrity matters.

They worked just fine. The clock speed was about 2MHz.


------------------------------------------
"If it don't work in simulation, it won't work on the board."
Expert Contributor
gszakacs
Posts: 5,263
Registered: ‎08-14-2007

Re: Been there, done that, worn out the t-shirt!


rcingham wrote:

As a recent graduate about 30 years ago, I co-designed and built a pair of ASIC emulators using discrete logic chips on a group of 3U single Eurocards (same size as yours) in 19" rack. They were wired - no PCB - as were the inter-board-connector connections. Some of the wires must have been about a foot long. No great regard was paid to signal integrity matters.

They worked just fine. The clock speed was about 2MHz.


In those days the minimum rise time of discrete logic was about 1 ns, and typical was probably

3 or more ns.  Most gates of that era would ignore glitches much less than about 3 ns.  None

of these statements are true for CoolRunner CPLD's.  Still you should be able to work with long

wires if you use series termination on any wires that need to have clean edges and make sure

to add the additional settling time delays when calculating setup requirements for synchronous

signals that don't need termination (typically three flight times of the wire) .

 

-- Gabor

-- Gabor
Expert Contributor
eteam00
Posts: 7,505
Registered: ‎07-21-2009

CPLD output buffer SLOW slew rate

2.  Reduce signal drive current or "strength" -- this is essentially the same as series termination, it increases the output impedance of the signal driver.  It also reduces the rise/fall time, which helps moderate signal reflections.

 

In the world of Xilinx CPLDs, this would be implemented by placing the following line of text in the project .UCF file (for each CPLD output pin):

 

NET mysignal SLOW; # SLOW stipulates that the slew rate limited control should be enabled.

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Super Contributor
rogerk8
Posts: 165
Registered: ‎05-28-2011
0

Re: CPLD output buffer SLOW slew rate

Hi Bob!

 

What a creative and fantastic idea! Thank you!

 

I will however begin with my already generated *.jed-file. If I get problems I will try to implement your idea.

 

I have decided to use my layout as is. This means that the 1ft input wires stands (CPLD output wires are a bit shorter).

 

I will preliminary not involve any terminations whatsoever. Except for CP input. Thank you for that tip!

 

Take care!

 

Best regards, Roger

PS

I was about to buy the euroboards today but there was no time left after work.