CPLDs

[eteam00]

But how is a clocked F/F implemented in the CPLD then?

CPLDs are CMOS devices.  To a first approximation, this is a good representation of a CMOS FF circuit.  At a more abstract level, it's two 2:1 MUXes, back to back.  First MUX is the master latch, the second MUX is the slave latch.  Together, it's an edge-triggered FF.

- Bob Elkind

[rogerk8]

Hi Gabor!

How do I set a KEEP constraint? Still interested in my obsolete design as you can see...

Kind regards, Roger

[eteam00]

I have decided to try designing a CPU in CPLD technology

Have you read about PicoBlaze?  There is a version designed for CoolRunner II CPLDs.

Start here.  You'll need to register and enter your secure sign-in.

-- Bob Elkind

[gszakacs]

---

rogerk8 wrote:

Hi Gabor!

How do I set a KEEP constraint? Still interested in my obsolete design as you can see...

Kind regards, Roger

---

Hi Roger,

You'll need to check out the Constraints guide which is available from the Help menu

of the ISE project navigator.  I don't generally design with schematics these days,

having opted to use Verilog instead.  So the actual method of applying the constraint

will be different since it is in the source and therefore depends on the design entry

method.  I believe that for a CPLD a KEEP constraint on a net, like the output of

your inverter feeding the two 3-input NAND gates, should force the inverter to use its

own macrocell rather than being mashed together into a single macrocell with

the NAND gates.  It might make sense for you to look through the XPLA3 family

data sheet to see how the macrocells are implemented.  This can give you an idea

of how your "gates" end up in the final design.

I seem to remember a very elegant D flip-flop block diagram in the original TTL data

book from Texas Instruments (yes I'm also grey on top like Bob and have been

designing since the days before programmable logic using pencil on vellum) that

used 6 3-input NAND gates to form one 7474 type D flip-flop with asynchronous

set and clear.  It's not obvious that even those flip-flops actually used the circuit

shown in the block diagram.  Other manufacturers show representations of

the D flip-flop using transfer gates (like a 74125 tristate buffer), which is probably

closer to the CMOS implementations.  Nowadays, most semiconductor manufacturers

assume you know the behavior of a D flip-flop and don't actually show the

construction in their data sheets.  In some cases the information is proprietary,

but in all cases the idea is that you only need to know the behavioral model

in order to use the device.  I suspect that Xilinx will not divulge the actual

structure of their flip-flops.  Rest assured, however that they are designed to

work very well in terms of setup and hold timing, metastability resistance,

and propagation delay.  Any attempt to use the combinatorial logic elements

in a CPLD or FPGA cannot come close to the performance of these flip-flops,

and if you're not careful (as you've already found out) results in something

that doesn't work at all.  I'm not saying that it isn't interesting to build sequential

logic from gates.  I've done it myself when I was using PAL16L8's and needed

a single flip-flop with unremarkable characteristics.  I just don't see how designing

sequential logic from gates will help you in your endeavor to make a CPU.

You're better off learning how to best use the resources available in your

CPLD.  Using multiple macrocells to build a simple flip-flop wastes a lot

of these resources.  In my early design days I would always look through the

part catalogs to see which MSI TTL devices could implement a significant

portion of my design.  This didn't mean that I couldn't design the function from

gates.  It's just good design practice to minimise the number of parts in

a system.  For programmable logic, this still holds true in that it's beneficial

to fit your design in the fewest chip resources.  This allows you to use the

smallest, cheapest part to get the design done.  And implementing a design

in a way that minimises on-chip resources holds as much fun and challenge

as learning how to build it from simple gates.

I wish you good luck in your design endeavors.  Hopefully the challenges of

designing with programmable components (and not against them or in spite

of them) will hold your interest and help you to succeed.

Regards,

Gabor

[eteam00]

I believe that for a CPLD a KEEP constraint on a net, like the output of your inverter feeding the two 3-input NAND gates, should force the inverter to use its own macrocell rather than being mashed together into a single macrocell with the NAND gates.

From the ISE Language Templates menu, under UCF > CPLD > Optimization > KEEP:

# KEEP prevents a net from being optimized forward into a MC Pterm.
 NET mysignal KEEP;
# Families: All CPLD.
# Applies to any signal except input pads.

Here's an alternative to a 'KEEP' constraint:  Make the intermediate term an output signal.  Might work!

yes I'm also grey on top like Bob and have been designing since the days before programmable logic using pencil on vellum

Did I ever tell you about the licensing fees for stone tablets and chisels?  That's when design tools really were tools.  The design tools were supplied by Apollo -- and we're not talking about the workstation outfit, we're talking about the Mt. Olympus Apollo.  Ah yes, the days of my youth...

I, too, abused PLDs at one point in my long and ?? career.  My favourite MSI 'can do most anything' devices were 8:1 decoder and dual 4:1 multiplexer.  74138 and 74153, I believe.

-- Bob Elkind

[rogerk8]

Hi Gabor!

I thank you for your essay. It was very fun and interesting to read. I recognize that I don't know much about modern CPLD programming. I don't even know what a macrocell is, it's implementation or it's capacity. I am just a stupid beginner who has a crazy but fun idea. The reason for me being stubborn about the obsolete FF design is because I already have my CPU designed on paper/Wikibooks using nothing but gates. And I just want to implement it in my target CPLD. It is however not said that I must implement it that way. In view of what both you and Bob have said it seems like a good idea to make fully use of the device capacity instead of stubbornly continue my journey in the technology of the 70's.

Just read about macrocells on Wikipedia. There was not much said but I think I am a little bit wiser now because the definition of a macrocell seems to be a "prefabricated array of higher-level logic functions". But I kind of knew that.

Next small step is to design a byte-register using my upgraded SR-FF (using predefined JK-FF's). I know there are fredefined registers too but I kind of suspect that they won't perform my exact wishes. A bigger problem here is actually how to schematically design my upgraded FF at low-level instead of top-level. But I will make use of the ISE Help for this.

Thanks again for the effort and interest in helping me!

Kind regards, Roger
PS
If you like you may view my crazy design at http://sv.wikibooks.org/wiki/CPU_design . It is unfortunatelly written in swedish but you might appreciate some pictures. Furthermore, the book is quite messy and not that accurate (I recommend you to jump to part2 i.e del2).

CPU 1.2 will preliminary not have neither a multiplier nor a divider. This is partially because I don't know how to implement them, partially that I've played with the thought of shifting left as multiplying and shifting right as dividing (by multiples of two which may or may not be possible to approximate in SW).

[eteam00]

Just read about macrocells on Wikipedia. There was not much said but I think I am a little bit wiser now because the definition of a macrocell seems to be a "prefabricated array of higher-level logic functions". But I kind of knew that.

Macrocell specifics vary from one family of CPLD to another. For the XPLA3 family, DS012.pdf, Figure 5.

I am just a stupid beginner who has a crazy but fun idea. The reason for me being stubborn about the obsolete FF design is because I already have my CPU designed on paper/Wikibooks using nothing but gates. And I just want to implement it in my target CPLD.

Have you read Don Quixote lately?  :)

-- Bob Elkind

[rogerk8]

Hi Bob!

Once again I thank you for your kind and funny reply. I laughed aload. I have much to learn! But I read the macrocell part of the link you thankfully supplied and I actually got somewhat more wiser. But I don't know how to use the information. Maybe it would be better if I actually read Don Quixote :-)

Anyways, I understand what you mean. But I am a stubborn man as you might have noticed. I am not even sure that I will use the upgraded version of my FF. I might want to implement it EXACTLY as I have planned (using the KEEP constraint). But I don't know. Who is actually interested in HOW you implement stuff? Isn't the goal the most interesting part? Not the way you got there, I mean. For me it is the way you got there, but for others? No, I think I will make use of the predefined logic functions as much as I can and afterwards my pride will have to shift from the actual implementation to the result.

It is fun to chat with you experts and I am moved about the interest and effort you put into my problem. It inspires me! And I know that my project is obsolete in many ways. But I really don't care. I will build my CPU in one way or the other. And while it for certain won't be able to compete with Intel, I really don't care. My far away goal is to build a computer from scratch. And something like MS-DOS to superwise it. Rediculous, don't you think?

Kind regards, Roger Knopp

[rogerk8]

Hi Bob!

Now I have managed to schematically design an 8-bit register with my own upgraded symbol of a SR-FF. It was actually kind of hard to get ECS to involve my symbol but finally I managed. Don't ask me how but this fact made me very happy. I was using the ECS help but understood almost nothing :-)

It seems like I'm kind of getting there but still it's a long way to go. I'm attaching the schematics.

Take care!

Kind regards, Roger Knopp

PS

I read your links about CMOS circuits. It was very interesting but I knew the basic parts, that is how a CMOS inverter is implemented, but when it came to transmission gate FF's I kind of lost the trail.

[eteam00]

but when it came to transmission gate FF's I kind of lost the trail.

That's OK, Xilinx takes care of the details for you, but only if you let them.

-- Bob Elkind