Re: Where's Roger's parts?

eteam00 · ‎07-21-2009

If I understand this correctly it is however not required to rerun compilation and so fort if I decide to use a faster device.

Correct, as far as I know.

I'm honored that you think so good of me that you suggest even faster devices.

Nothing but the best for you, Roger! Besides, you're paying for the parts.

-- Bob Elkind

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rogerk8 · ‎05-28-2011

Hi Bob & co!

I'd just like to let you know that my pet project is proceeding, however slowly. I have recently finished the tedious microprogramming part. Now I am reading Motorola S-record protocol (SREC) because that is what I have been recommended to do if I am to succeed in programming these old (and slow...) PROM's. At this point I however do not fully understand the point in using SREC because what is wrong with one address and one byte per row (except for configuring the burner for actually used memory type such as address and data width, burn voltage etc).

I have another reason for writing to you. I have detected something which seems to be wrong in the XPLA3 Family Manual, titled Coolrunner XPLA3 CPLD (do unfortunatelly not know how to make it "click-able"). If you turn to page 7 and the right paragraph, the last sentence high up on the page is:

"The Port Enable pin must be a low logic level during the power-up sequence for the the device to operate properly"

In the middle of the next paragraph it is however explained that Port Enable (PE) may be interpreted as "JTAG Enable". Which of course means that if PE is high the dedicated I/O's are used as JTAG. In the beginning of the next paragraph it however says:

"If the JTAG pins are not required as I/O, port enable should be permanently tied to ground".

This is confusing because if you pull PE low JTAG is disabled and the dedicated ports may actually be used as general I/O's (?)

I think the last sentence should be changed to something like:

"If the JTAG pins are not required, port enable should be permanently tied to ground which means that the CPLD will have to be programmed off-board".

Mainly omitting the "as I/O".

Have I understood this correctly?

Finally, I happily read in this same manual that unused inputs are configured as inputs with weak pull-ups. This means that I may design the layout with the five last and preliminary unused PROM outputs directly connected to the CPLD. Ready to be configured for MUL/DIV at a later time. It is however not recommended by Xilinx to do so. But I will do it anyway :-)

Take care!

Kind regards, Roger Knopp

PS

Thanks for the tip on where to find my CPLD. I am even able to buy only one. This gives me inspiration for future work!

eteam00 · ‎07-21-2009

This is confusing because if you pull PE low JTAG is disabled and the dedicated ports may actually be used as general I/O's (?)

With PE pin tied LOW:

JTAG is disabled if the CPLD was programmed to use the JTAG pins for user I/O ("Reserve ISP pins" option unchecked).

JTAG is enabled if the CPLD was programmed with "Reserve ISP pins" option checked (default).

This Answer Record may be interesting to you.

-- Bob Elkind

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rogerk8 · ‎05-28-2011

Haha!

Just want to say thanks even though your answer was kind of short. You don't say much, do you? Me, I need more beer :-)

As always,

Kind regards, Roger

eteam00 · ‎07-21-2009

... your answer was kind of short.

Were your points answered? Or do you still have questions (or disagreement)?

-- Bob Elkind

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rogerk8 · ‎05-28-2011

Your answer was perfect. As always. KR/Roger

eteam00 · ‎07-21-2009

Your answer was perfect. As always. KR/Roger

Another beer for my friend Roger, please!

-- Bob Elkind

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rogerk8 · ‎05-28-2011

Hi Bob!

Just want to let you know that my pet project is progressing.

I have had the rare opportunity to be ordered to repair EPROM-burners at work. It showed that there was no fault with the units just my technical supervisor who showed that they did not work when he turned on the power. The units (Dataman SX) just needed some reset whith a special kind of pointed tool to actually start. I am real bad at english :-)

On the other hand, I got to configure my computer (MS HyperTerminal) into handling Motorola S-record. So now I know exactly how I need to configure my data for PROM/Dataman usage.

Now I just need some working space. Right now I am sitting on my skin leathered foot stool and the working hight is not that good. I am on the verge of getting the rest of my furnitures through ikea (recently moved to a new apartment).

I have decided to order the fastest version of CPLD in spite of the fact that the chosen EPROM's will limit the maximum frequency to somewhat 3 MHz.

It is hard o increase the frequency. I mostly want it to work, even if that means "dc".

Take care Bob!

Kind regards, Roger Knopp

eteam00 · ‎07-21-2009

When your design makes you rich and famous, Roger, just remember the little people who helped you along the way...

-- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

rogerk8 · ‎05-28-2011

Hi Bob & co!

I have recently finished my preliminary schematic of my CPU with an extremely primitive built-in test bench. I am attaching it for your hopeful enjoyment.

Me, I think it looks rather nice. The huge question is however now if it will work or not. I am optimistic that it will work for some intructions but probably not for all. This is because of the human factor.

I have tuned down the maximum frequency to some 100kHz. This will be generated by a simple relaxation oscillator. No chrystal will preliminary be used (the minimum frequency for a chrystal seems to be some 1MHz).

I am on the verge of creating a real schematic using a professional CAD tool at work. With the use of that tool I will be able to both generate a component positioning schematic and a PCB layout.

I use LED's everywhere for debugging purposes. There are over 100 LED's in my design (none of them however draws more than 1mA which I experimentally have found is more than enough for indication).

Take care!

Kind regards, Roger

PS

I recon that the clock inputs are not 5V tolerant. I have serched the data sheets for information regarding this but cannot find it. This is because I wanted to use a 5V crystal IC. This has however been discarded in my current design so it really doesn't matter now. But it would be nice to know.