07-09-2012 10:04 AM
I'm new to HDL and Xilinx products and wanted to learn about programmable Hardware, so I bought the CoolRunner II CPDL starter Kit and installed the Xilinx ISE10.1 software.
As a starting point I decided to use the guide "Programmable Logic Design - Quick start Guide May 2008" and went through the tutorial in chapter 4 to build a counter and led display.
I've worked through the tutorial and everything seems fine until I reached the stage of implementing the design on a CPLD.
The Synthesis step went fine with no errors, however when I tried to set up the correct pins, I ran into problems.
I've double clicked the Floorplan IO and the PACE tool opens with an error:
Error: HDLParsers 3562 - pepExtractor.prj line 1 Expecting 'vhdl' or 'verilog' keyword, found 'work'
A pop up error box:
PACE was unable to parse HDL source file C:/Documents and Settings\Tutorial\top.vhd
I enclose the top level vhdl file
07-16-2012 11:13 PM
I don't think the (automatically generated) VHDL file is the problem.
But the source path may be bad.
Xilinx tools are very sensitive to whitespace characters in paths, since many things are script based.
(especially when you are using something old as ISE 10.x)
Your project is in:
C:/Documents and Settings\Tutorial
which contains two whitespaces.
Try to work on a path that contains no whitespaces.
Have a nice synthesis