06-25-2012 11:50 PM
Right now I am going to design some interface (asynchronous oriented) and I'll realize it in XC2C256.
I used to design FPGA a lot with Verilog-HDL, so in my prevoius design, I tried to synchronize all the singals with one system clock.
But for CPLD, the architecture are different with FPGA, and there are only Flip-Flop in the IO pins.
1) Is there marked difference between FPGA and CPLD code design?
2) In CPLD, should I use more gates(e.g., or, and, xor...) instead of Flip-Flop?
Solved! Go to Solution.
06-26-2012 05:38 AM
You can try to design the same way for the CPLD as you did for an FPGA. If you don't
run out of resources, then it's OK. Just remember that flip-flops are more plentiful in
an FPGA than a CPLD. Using a flip-flop in a CPLD without any preceding logic gates
essentially wastes the gates from that macrocell - sometimes. Note that I say sometimes,
because most modern CPLD's have a variable number of "product terms" per macrocell
and unused product terms can go into other adjacent macrocells that need them.
Also pipelining to increase throughput is different in a CPLD because it is the number
of product terms that determines how much logic you can have in one level rather than
the number of inputs. Still, for relatively simple designs that can fit into a CPLD you
can often get away with designing the logic as you did for an FPGA.
06-26-2012 08:10 AM
I am very glad to know that I can design my CPLD code as FPGA (Synchronous design, adding basic timing constraints, such as period, OFFSET IN and so on...)
We all know that the architecture is different, we just let ISE to translate it.
Is there any document about how to design Verilog code in CPLD?
Is this important in our verilog design?
06-26-2012 09:39 AM
Designing for a CPLD vs FPGA is looked at as "optimization" by the normal text books.
Perhaps if you come across a good document on designing with CPLD's you can
post a link here. Otherwise I'd say to look through the README First: Help for new users,
but there's not a whole lot on CPLD design there (yet). Looking around, there are a lot
more resources available for designing with FPGA's than for designing with CPLD's.