04-04-2012 03:20 AM
I am developing network device with 10-Gigabit Ethernet MAC v9.1.
Overflow occurs in the Transmit Fifo (tx_fifo.v)
The reason is that ....
"tx_start" is sened to MAC core, but acknowledge ("tx_ack") does not come from MAC core. (file is attached)
why acknowledge ("tx_ack") does not come ??????
please help me..!!!!!!!
04-09-2012 10:30 AM
I'd recommend comparing all of the inputs to the core your simulation to the example design simulation provided when the core is generated. Check that all of the input clocks are provided and that the global reset and tx reset are not asserted and that the tx is enabled.
04-10-2012 12:24 AM
I checked all signals but i did not find something wrong.
my simulation result is good. No Problem!!
problem occurs only fpga test.
several packets are transferred very well but the transfer is always interrupted because of no "tx_ack".
i have no idea !!!
04-16-2012 10:40 AM
Is the issue resolved by issuing a core reset or be asserting tx_start again? I don't see any issue with the tx user interface in the attached waveform.
I would recommend verifying timing is being met for the core and open up a support case to explore further if you are still encountering issues.