Connectivity

[strangesteve]

Im working on a project using the 10G MAC core in a virtex 7 project within edk, I know the new version of the 10G MAC uses AXI streaming interface, what is the best way to convert it to memory mapped AXI interface? CDMA, VDMA, AXI DMA, or just usung a datamover core or the 'axistream to fifo' core?  Leaning toward the AXI DMA but wanted to see what others are using - its a shame the core wasnt build using a memory mapped AXI interface to begin with.

Ive worked on a V6 design using a 10G Ethernet MAC core that used the old LLFIFO interface, but deciding the best way to tackle the AXI MM to AXI S interface eludes me.. anyone have any suggestions on best /easiest approach?

In my last design witht the 10G MAC (LLFIFO) interface on V6 we didnt need a dma at all due to special logic processing all the packets, so any info on how to use the newer AXI Streaming version within EDK or even on the best way to use it with the regular AXI interface would be great.

[johnmcd]

The axi_dma block is the best in this case. It includes additional axi control and status streams.

[strangesteve]

Cool, thats kind of what i thought but wanted to see if there were any other options. But thank you, was also curious if ISE 14.1 will contain axi stream bus capability (and possibly an streaming to mm axi bridge)? 

[johnmcd]

For your first question, I'm not the one to ask. Talk to your FAE. For your second question, look at the datamover. It's been in edk for a while. It looks after breaking up bursts across 4KB alignment boundaries and it supports store/forward. For stream to mm, I place a coregen axi fifo on the stream side so that I can buffer enough data to support one burst so that the mm interface doesn't get held up while waiting for more streaming data.