Connectivity

[angenghian]

Is there any issue using 125MHz as ref clk for V5 (SXT) PCIe Endpoint Block Plus?

While the Core Gen only allows 100MHz or 250MHz, I think the clk can be changed to 125MHz by modifying pcie_gt_wrapper and pcie_clocking.

However, I wonder why the Core Gen does not want to support 125MHz. Is it because of practical issue like jitter exceeding PCIe spec?

[mcgett]

Using 125 MHz or 250 MHz as the reference clock would improve the RX and TX performance of the design.  The 100 MHz is the de-facto standard set by Intel and the PCISIG.

You will need to modify the attributes on the MGTs that are used by the PCIe core to support the change in the reference clock and maybe the pcie_clocking block (I haven't looked at the internal to know what is in it), but once this is done it should work fine.

If you are using a system that does not have the same clock used for both endpoints of the PCIE block you may run in to some interoperability issues if one of the endpoints doesn't have a reasonable size elastic buffer or doesn't support clock correction.

[luisb]

One furthering thing to add.  After you make all these changes, I highly recommend a simulation.  You'll save a lot of time and you'll be able to ensure your internal clock rates are correct.